It's more CISCy than MIPS/RISC-V. It does a reasonably good job of having complex instructions that closely match real world patterns, as opposed to some of the crufty bits of x86 that are complex... and useless.

The "crufty bits of x86" did "match real world patterns" when they were introduced (and neither ARM nor MIPS even existed)... and some still have surprising uses: https://news.ycombinator.com/item?id=8477254

But in general, these more complex instructions are where most of the microarchitectural optimisation happens. The BCD instructions mentioned in the above link were originally implemented in microcode and took dozens of cycles; for example, AAD took 60 cycles on an 8086, but only ~4 on a Skylake (and can be scheduled in parallel with the uops of other instructions) --- despite the little use it has today. A look at instruction timing tables[1] shows that the common idea of little-used instructions receiving no optimisation or even becoming much slower with each new processor generation is mostly false (there are exceptions, like the ill-fated P4.)

[1] http://www.agner.org/optimize/instruction_tables.pdf