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A comment on In-Depth View of Wave Computing’s DPU Architecture, Systems.

Re:In-Depth View of Wave Computing’s DPU Architecture, Systems by deepnotderp on Friday August 25, 2017 @12:59PM (#15100111)
Fairly certain a true dataflow machine doesn't have 50% the amount of instruction RAM as it has data RAM.

Also putting all the "tensors" (I assume this means activations and weights?) into the external memory is downright dumb.

Only having 16MB of memory on die is also probably not a wise decision.

The use of GALS is certainly interesting though.

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Re:In-Depth View of Wave Computing’s DPU Architecture, Systems by feelix on Saturday August 26, 2017 @01:25AM (#15104202)
Are you qualified to make these criticisms?
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Re:In-Depth View of Wave Computing’s DPU Architecture, Systems by deepnotderp on Saturday August 26, 2017 @03:21PM (#15106914)
Absolutely not, I'm very biased (see my profile) :)

I do think the criticisms are valid regardless though. Data movement is far more expensive than computation, so having so little on-die memory is almost definitely a bad decision.

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