Re:An FPGA-friendly 32-bit RISC-V CPU implementation
by zokier on Wednesday July 19, 2017 @04:36PM
(#14807674)
Is either AXI4 or APB3 usable as external bus (like PCI(/e)), or are they intended for on-die communication?
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Re:An FPGA-friendly 32-bit RISC-V CPU implementation
by monocasa on Wednesday July 19, 2017 @09:24PM
(#14809390)
They are usable externally. The Realview boards use it to connect a CPU chip with an external northbridge, but it's really rare. Even in that case, it's just because the Realview board is meant to prototype SoCs with the help of an FPGA.
Re:An FPGA-friendly 32-bit RISC-V CPU implementation
by duskwuff on Thursday July 20, 2017 @01:02AM
(#14810111)
Usable, but only barely. As AXI / APB3 are intended for on-die communications, they lack the line coding and error correction used by other busses like PCIe or SATA. On the upside, though, they take a lot less area to implement.
Re:An FPGA-friendly 32-bit RISC-V CPU implementation
by monocasa on Thursday July 20, 2017 @11:53AM
(#14813546)
That's more a distinction between serial and parallel buses than on-chip/off chip. If you're not pumping a single signal to gbps speeds, you don't need the clock recovery and ECC that serdes style connections imply.
It all depends on your use case.