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A comment on The Mill CPU Architecture: Switches [video]. Parent comment

Re:The Mill CPU Architecture: Switches [video] by _chris_ on Tuesday July 18, 2017 @09:28PM (#14801463)
"We postulate that the original study produced good results because it evaluated the new scheduler in a machine whose performance bottleneck lay outside the execution core. The problems introduced by the steering logic were, as a result, hidden."

Any new microarchitecture needs to first answer that big question -- how is the core going to deal with memory?

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Re:The Mill CPU Architecture: Switches [video] by deepnotderp on Tuesday July 18, 2017 @09:33PM (#14801487)
Fun fact, the Mill's proposed method for hiding that latency, "deferred loads" has already been done by Duke's Architecture Group: http://people.duke.edu/~bcl15/documents/huang2016-nisc.pdf (warning PDF link).

The big gain? A measly ~8%.

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Re:The Mill CPU Architecture: Switches [video] by cwzwarich on Tuesday July 18, 2017 @09:35PM (#14801504)
This doesn't decouple across function calls like the Mill claims to, right? Although doing that optimization on existing C/C++ programs will be difficult.
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Re:The Mill CPU Architecture: Switches [video] by deepnotderp on Tuesday July 18, 2017 @09:38PM (#14801518)
I don't think that's enough of a difference, YMMV, but nothing indicates that it should.
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