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Re:Exploring DynamIQ and ARM’s New CPUs: Cortex-A75, Cortex-A55 by pedroaraujo on Monday May 29, 2017 @03:46AM (#14437941)
It's not like ARM randomly slaps features just for the fun of it. These features are carefully modeled and studied before released into the market.
Re:Exploring DynamIQ and ARM’s New CPUs: Cortex-A75, Cortex-A55 by Aissen on Monday May 29, 2017 @04:04AM (#14437989)
Of course every design team wants to think it works this way. But the big/little mess (at the OS level), and the fact that Apple is beating them at their own game (like Qualcomm was, at the time) is a proof that it's not that simple.
Re:Exploring DynamIQ and ARM’s New CPUs: Cortex-A75, Cortex-A55 by samfisher83 on Monday May 29, 2017 @10:15AM (#14439175)
ARM needs to make a design they can sell to a lot of different people. Apple has one customer Apple. Their chips are larger and they have more transistors to play with and they can optimize the number of cores to what they want. If you have more transistors you can add more features like decoders, alus, cache, or whatever which make your chips faster. So it isn't fair to say Apple beat ARM at their own game.
Re:Exploring DynamIQ and ARM’s New CPUs: Cortex-A75, Cortex-A55 by pedroaraujo on Monday May 29, 2017 @04:40AM (#14438107)
An ARM CPU is not exactly a self contained system like an x86 CPU, it is very dependent on the rest of the SoC.

Qualcomm and Apple have their own tricks which work very well in their platform alone but they wouldn't be able to simply plug out their ARM implementation and sell it as a really optimized system without their own SoC.

Re:Exploring DynamIQ and ARM’s New CPUs: Cortex-A75, Cortex-A55 by dooferlad on Monday May 29, 2017 @08:21AM (#14438731)
The rest of the SoC plays a huge part, just like the architecture of a PC does. My personal mantra when thinking of how to get the most out of a CPU is "feed the beast" since idle time is the killer. In the most simplistic terms your L1 caches need to be big enough to hold the program you are running and the data it is using. You can hint to the CPU about what data you will need and get it to preload and branch prediction does a similar job for fetching instructions and avoiding branch misses.

I for one like to see big caches in SoCs, but the cost of putting it there needs to be balanced against the performance requirements of the product (no point having a bigger chip than you need). There is also the numbers game of 64 bit / number of cores / RAM etc which are easy to parse but difficult to understand. An irrelevant number of consumers care about IPC and time taken to wake a core or switch a workload between cores, so great innovations like big little are used as marketing numbers rather than to tune a SoC to its best performance. I would like to see 1 big, 2 little cores and more cache myself.

So what do Apple have? Lots of cores? No. If you build an 8 core SoC and can't keep those cores running then you have listened to marketing.

Re:Exploring DynamIQ and ARM’s New CPUs: Cortex-A75, Cortex-A55 by kevin_thibedeau on Monday May 29, 2017 @09:31AM (#14438993)
Intel does the same. Didn't prevent them from producing P4 or Itanium.