A working, transistor-scale replica of the MOS 6502 microprocessor

Re:A working, transistor-scale replica of the MOS 6502 micro... by mrob on Sunday May 21, 2017 @10:57AM (#14387585)

NMOS logic is made from a passive pull-up resistor on top of an active pull-down network. An NMOS gate can switch from high to low very quickly, because the pull-down network connects the output to ground via only its very small on-resistance. The input capacitance of the subsequent gate discharges through that small resistance quickly. But NMOS switches from low to high much slower, because that gate capacitance has to charge through the higher resistance of the pull-up resistor. The pull-up resistance has to be relatively high, because otherwise the voltage would be divided roughly evenly when the pull-down network is turned on, which means the output voltage would be in the undefined region between low and high and the gate wouldn't work. There's also a trade-off between pull-up resistance and power consumption, with a stronger (lower resistance) pull-up using more power.

With CMOS, both the pull-up and pull-down parts are active, so one can be switched on while the other is off. There's always a low resistance path to Vdd or ground, and the subsequent gate capacitance can both charge and discharge quickly. The drawback is that it's harder to manufacture a chip with both N-channel and P-channel transistors.

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Re:A working, transistor-scale replica of the MOS 6502 micro... by psykotic on Sunday May 21, 2017 @12:46PM (#14388020)

The 6502 chip design used precharging for exactly that reason. You precharge to Vdd in phase 1 through a path with high drive strength and then in phase 2 only the fast pull-down network has to do any work if needed. The pull-up network is still there to prevent floating and hence needs to be ratioed against the pull-down on-resistance to pass a strong 0, but the pull-up resistance no longer sets the low-to-high switching time. The main limitation is that it can only handle monotonic logic, so you may need to interpose static inverting logic stages between your precharge logic stages.

And in standard chips nowadays, you can still find transmission gate logic (complementary pass transistors so you can pass both strong 1s and strong 0s), pseudo-NMOS logic (using a boring old enhancement mode PMOS transistor tied off to ground as a pull-up resistor) and domino logic (precharge logic with interleaved CMOS stages) in critical datapath circuits, so even in a bog standard CMOS process there's room for trickery.

> The drawback is that it's harder to manufacture a chip with both N-channel and P-channel transistors.

Yeah, and CMOS wasn't competitive for higher speed chips until the 80s (the 68000 was NMOS based until 1985 and some higher end processors eschewed MOS and used bipolar ECL). CMOS had been around for a good while at that point but was mainly used for applications like battery-powered watches and calculators where static power draw was more important than speed. The 65C02 (a CMOS version of the 6502 with a few other features thrown in) came out in 78 and was competitive in speed to the original 6502, though it was originally designed for a customer for use in calculators, but of course ended up being used in numerous home computers.

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