Just a question, why are you against RISC-V?

I quite like RISC-V and think it's elegant and simple, but maybe I'm wrong :)

My biggest complaint about RISC-V is its lack of condition codes. This is just too puritanical. I think ARMv8 strikes a nice balance here. Leaving something out that both ARM and Intel provide seems pointlessly austere.

As was pointed out in the A History of Modern 64-bit Computing cite, both RISC and Itanium show an academic bias. Yes, RISC-V is elegant and simple and that helps in a one semester upper div architecture class. But that doesn't help you much outside of a one semester upper div architecture class.

So what do you tangibly get with that elegance and simplicity? You aren't going to write RISC-V assembly; compilers are better especially for such a regular and spare ISA. This is 2017 and LLVM has been a thing for quite some time. Compilers are not a big deal.

Lower power? Chip area? How much lower power and chip area are we talking about?

I'm not too sure about the "academic bias" point, since modern "CISC" CPUs are essentially "CISC on RISC" and essentially RISC already.

That being said, greater efficiency is the main point, it's not too difficult to get a RISC-V core that beats (albeit marginally) an equivalent ARM core.

Optimizing compilers can often be difficult though, especially if you want to use novel modifications to the backend to make things more efficient.

No, Skylake is not a RISC internally. Find something from the Intel Optimization Manual or their patents saying that. I been over this already. μops are hundreds of bits wide. Ain't nothing reduced about that.

Read up on horizontal microprogramming. A RISC ISA is an encoding with an opcode. A μop is really just a long set of fields with some bits clocking some FUs on and others off. There is no decoding; there is no opcode.

I'm aware of horizontal microprogramming,and I checked again but I still don't see your point. Maybe link a reference?

Smotherman.

A complete macroinstruction is executed by generating an appropriately timed sequence of groups of control signals (micro-operations).

http://www.frsn.utn.edu.ar/tecnicas3/manuales/Microprogrammi...

Originally, RISC cpus were hardwired but they are general purpose ISAs. RISC-V is fixed 32b ISA but has multiple formats controlled by an opcode.

https://image.slidesharecdn.com/20160130deckyfosdemportinghe...

Original microprogrammed CPUs had a writeable control store (WCS). Modern processors translate CISC instructions into μops and cache this translation. The difference is the μop cache (μstore) vs WCS. FWIW, Skylake also has a WCS for obscure instructions.

Microinstructions, μops, do not have an opcode. They are not decoded. Bits in a horizontal μop gate logic on/off directly.

The RISC-V people do say RISC-like.

https://www2.eecs.berkeley.edu/Pubs/TechRpts/2016/EECS-2016-...

And even that's wrong. But then they never even define what a RISC is. So RISC-like could be anything.