Read up on horizontal microprogramming. A RISC ISA is an encoding with an opcode. A μop is really just a long set of fields with some bits clocking some FUs on and others off. There is no decoding; there is no opcode.
A complete macroinstruction is executed by generating an appropriately timed sequence of groups of control signals (micro-operations).
http://www.frsn.utn.edu.ar/tecnicas3/manuales/Microprogrammi...
Originally, RISC cpus were hardwired but they are general purpose ISAs. RISC-V is fixed 32b ISA but has multiple formats controlled by an opcode.
https://image.slidesharecdn.com/20160130deckyfosdemportinghe...
Original microprogrammed CPUs had a writeable control store (WCS). Modern processors translate CISC instructions into μops and cache this translation. The difference is the μop cache (μstore) vs WCS. FWIW, Skylake also has a WCS for obscure instructions.
Microinstructions, μops, do not have an opcode. They are not decoded. Bits in a horizontal μop gate logic on/off directly.
The RISC-V people do say RISC-like.
https://www2.eecs.berkeley.edu/Pubs/TechRpts/2016/EECS-2016-...
And even that's wrong. But then they never even define what a RISC is. So RISC-like could be anything.
That being said, greater efficiency is the main point, it's not too difficult to get a RISC-V core that beats (albeit marginally) an equivalent ARM core.
Optimizing compilers can often be difficult though, especially if you want to use novel modifications to the backend to make things more efficient.