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Re:How Many X86-64 Instructions Are There Anyway? by pcwalton on Sunday April 30, 2017 @05:35PM (#14233977)
> By ~2000 most RISC architectures were dead (Alpha, SGI, ...) with only POWER and SPARC surviving in their niche markets.

You forgot ARM, which is a major omission.

> In the end, x86 won, because x86 had the bigger market with more money in it.

It's not the end yet. :) x86's dominance in the future is hardly assured, and in fact if you measure by total number of microprocessors sold, x86 is a small niche--300-400 million sales per year compared to 15 billion ARM chips sold.

Re:How Many X86-64 Instructions Are There Anyway? by jcranmer on Sunday April 30, 2017 @05:57PM (#14234077)
ARM instructions let you do r1 = r2 + (r3 << r4) if CC, and that's just basic instruction set. That's as much an affront to RISC as x86 is.
Re:How Many X86-64 Instructions Are There Anyway? by smitherfield on Sunday April 30, 2017 @10:28PM (#14235205)
That's not accessing memory, so there's no reason it couldn't be (reasonably) efficiently pipelined without decoding to µops.
Re:How Many X86-64 Instructions Are There Anyway? by pcwalton on Sunday April 30, 2017 @06:21PM (#14234185)
Not in AArch64 IIRC.
Re:How Many X86-64 Instructions Are There Anyway? by Questron on Monday May 01, 2017 @06:39AM (#14236633)
Only the condition code was removed. Otherwise the parent is right and there really is an enormous amount of instructions. Fortunately less than intel, but still a lot.
Re:How Many X86-64 Instructions Are There Anyway? by pcwalton on Monday May 01, 2017 @04:16PM (#14241114)
I don't think you can do variable length shift with an arithmetic instruction in AArch64 either: only immediate shifts.
Re:How Many X86-64 Instructions Are There Anyway? by dom0 on Sunday April 30, 2017 @05:40PM (#14233997)
So? Samsung also sells a lot more smartphones than Apple, yet Apple makes far more profit from them. You can't pay R&D with revenue.

There are probably more PowerPC chips sold via laser printers and such than x86 chips. Conversely, 8051 derivates probably outnumber all of these. So what. Meaningless argument.

Re:How Many X86-64 Instructions Are There Anyway? by pcwalton on Sunday April 30, 2017 @05:50PM (#14234045)
It's pretty hard to make an argument in 2017 that Intel is in a better economic position than its mobile competitors by focusing on the PC market.
Re:How Many X86-64 Instructions Are There Anyway? by dom0 on Sunday April 30, 2017 @05:37PM (#14233984)
This thread is about high performance. I.e. desktop, workstation, server processors.

> Why are x86/64 processors used for most high performance applications then?

Also ARM, the architecture where most cores have between three and four distinct frontends, hardly qualifies as R ISC.

Re:How Many X86-64 Instructions Are There Anyway? by pcwalton on Sunday April 30, 2017 @05:44PM (#14234012)
Even with the complexity of Thumb-1, Thumb-2, and NEON, I'd give the edge to ARM in simplicity. At least the instruction encodings for ARM make sense, even today. x86 instruction decoding is absurd.

More importantly, ARM has a way to massively reduce its decoding complexity, via AArch64. AArch64 is a separate RISC instruction set, with room explicitly left in the design for dropping 32-bit ARM in the future (32-bit support is optional, though in practice today everyone includes it). ARM is effectively in the process of making a transition to a more RISC-like ISA, unlike Intel which has no realistic way to get there.

Re:How Many X86-64 Instructions Are There Anyway? by wolfgke on Tuesday May 02, 2017 @09:49AM (#14246262)
> Even with the complexity of Thumb-1, Thumb-2, and NEON, I'd give the edge to ARM in simplicity. At least the instruction encodings for ARM make sense, even today. x86 instruction decoding is absurd.

If you write down the x86 instruction encoding in octal, it makes a lot more sense:

> http://www.dabo.de/ccc99/www.camp.ccc.de/radio/help.txt

Re:How Many X86-64 Instructions Are There Anyway? by pcwalton on Tuesday May 02, 2017 @04:49PM (#14250441)
For the 8086, sure. But modern x86 throws in Mod R/M, SIB bytes, REX prefixes, VEX prefixes, Operand Size Overrides…