Turtles on the Wire: Understanding How the OS Uses the Modern NIC (2016)

Re:Turtles on the Wire: Understanding How the OS Uses the Mo... by shaklee3 on Monday April 03, 2017 @01:00AM (#14020688)

All good points, but keep in mind the 200gbps is somewhat of a gimmick since pcie3 will top out at 128gbps. It's useful for a redundant port, but you won't be pushing 200gbps for a while.

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Re:Turtles on the Wire: Understanding How the OS Uses the Mo... by en4bz on Monday April 03, 2017 @01:13AM (#14020731)

Apparently they have PCIe4 x16 and PCIe3 x32 models. Not sure if either of these exist at the moment but they so satisfy the PCIe bandwidth constraints.

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Re:Turtles on the Wire: Understanding How the OS Uses the Mo... by kev009 on Monday April 03, 2017 @04:11AM (#14021284)

They have one that is two PCIe3 x16 connections from one ASIC right now, it uses a ribbon cable :). That's janky, but it does work on currently available platforms. I've heard Mellanox will do a CAPI NIC, which is quite tantalizing.

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Re:Turtles on the Wire: Understanding How the OS Uses the Mo... by shaklee3 on Monday April 03, 2017 @09:23AM (#14022547)

Thanks, I didn't see that. But yes, that's weird. In regards to pcie4,I believe the power9 will be the first to have it, but I haven't seen a solid release date for that. Naples didn't look like it had it -- just more pcie3 lanes.

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