Anyway, if you actually trace the furthest bit of a ram chip to the CPU it's a longer path than you might think > 1 foot but < 3 feet.
As to my point tCL is a round trip latency and actually not that far from optimal. DDR is not designed for pure random access so much as cheap access to lot's of ram so yes there are many trade offs, but they are more reasonable when your close to hard limits.
Here is a picture, from the center of the CPU, to the bottom edge of the furthest part of the DIM then up. http://harddiskdirect.com/media/catalog/product/cache/1/imag...
PS: A DIMM is just over 5 inches wide and 0.7 inches tall so if was centered physically on top of a CPU that's 3 inches right there.
But, that's part of the CPU packaging, a signal needs to get to these pins on the bottom of the CPU and that takes time.
You're point isn't invalid but it's sort of misapplied. In fact the latency of DRAM on modern systems is dominated almost entirely by precharge time within the memory IC, which is about an order of magnitude slower than signal propagation. And it's not changing, either. DRAM cycles have been sitting at around 60 MHz for a decade and a half. We're dropping voltage as we shrink the cells, and so there's no net increase. Realistically signal propagation will never be the limit.