Yes, is it practical: No. You'd probably have to calculate (and know) all interconnect path delays for all solutions you want to try. You'd need to take into account not just the available gates but also their individual delays. I'd stick with emulation for now, though there are async 8051 processors which are extremely interesting due to their low power usage.[1]

[1]: http://ieeexplore.ieee.org/document/4519392/

definitely. plenty of literature on this. the problem, however, is how the delays are calculated. FPGAs have a lot more intermediate logic to determine which gates are connected to what, and that means intermediate delays that you need to account for.

not saying it can't be done or even that it's hard. just a different process.