Re:What happened to clockless computer chips?
by mycall on Monday February 27, 2017 @11:17PM
(#13751115)
Can typical FPGAs support async circuits?
Re:What happened to clockless computer chips?
by consp on Tuesday February 28, 2017 @03:55AM
(#13752351)
Yes, is it practical: No. You'd probably have to calculate (and know) all interconnect path delays for all solutions you want to try. You'd need to take into account not just the available gates but also their individual delays.
I'd stick with emulation for now, though there are async 8051 processors which are extremely interesting due to their low power usage.[1]
Re:What happened to clockless computer chips?
by imode on Tuesday February 28, 2017 @11:33PM
(#13761147)
definitely. plenty of literature on this. the problem, however, is how the delays are calculated. FPGAs have a lot more intermediate logic to determine which gates are connected to what, and that means intermediate delays that you need to account for.
not saying it can't be done or even that it's hard. just a different process.
there are ways of dealing with this. delay-insensitive circuitry, QDI circuitry, micropipelines...
if you're interested as to the "state of the art", as I learned it, look no further than Principles of Asynchronous Circuit Design[1], a fantastic book. a PDF[2] is also available. another fascinating piece of work are Micropipelines[3] by none other than Sutherland.
the main benefit for asynchronous architectures is their ability to be expressed in software. the primitives used (as you'll read) function very much like traditional software constructs based around control and dataflow. this is very easy when your entire architecture is based around pipelines, which can choose to hold and "re-transmit" data.
asynchronous design isn't dead or disadvantageous. we just forgot about it for some reason.
[1]: http://www.springer.com/us/book/9780792376132 [2]: http://www.orbit.dtu.dk/files/2775719/imm855.pdf [3]: https://pdfs.semanticscholar.org/b840/ae4b928964eff41206f89f...