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Re:The “high-level CPU” challenge (2008) by dnautics on Monday February 27, 2017 @05:04AM (#13743126)
Even #2 is questionable. I had a front row view of a company that made a chip very quickly and one way they were able to do it was to not bother emulating ASIC in FPGA. There are some very nice and open-source hardware development tools that basically obviate that need.
Re:The “high-level CPU” challenge (2008) by adwn on Monday February 27, 2017 @06:44AM (#13743527)
Once you get to the point where you need ASIC emulation, there are no open-source tools that are up to the task.

You don't need emulation for simple stuff like Bitcoin miners or other small and/or highly regular chips. You use it if you develop a large SoC taking tens of millions of dollars to develop. It takes months after finishing your HDL code and before you get the first silicon from the fab, and you don't want to wait that long before you can start testing your custom software.

So, no, #2 isn't questionable, it's routine practice. In fact, the largest FPGAs by Xilinx and Altera are structured explicitly with that use case in mind.

Re:The “high-level CPU” challenge (2008) by gchadwick on Monday February 27, 2017 @10:12AM (#13744765)
Emulation via FPGA or dedicated HDL emulator (a special supercomputer designed for running Verilog/VHDL, very fast, very good, very expensive) is also essential for functional verification of things like CPUs.

For example booting linux and running a simple application can take many billions of cycles. You simply can't simulate that many you need something faster (You can simulate a few billion overnight with an appropriate server farm, but that's across many tests using many simulator instances).

Re:The “high-level CPU” challenge (2008) by dnautics on Monday February 27, 2017 @05:22PM (#13748952)
Unless you're NVIDIA, Intel, AMD, or Qualcomm, Apple, Samsung (you get the idea) why would you ever want to build anything besides "small and/or highly regular chips"?

I think there's a lot of interest in designing "highly regular" chips. And it's definitely possible to go quite far with open source tools. I've seen a 16-core general purpose chip with full 64-bit IEEE FP, ALU, and memory instructions operating at 1 MHz (real speed) as a gate-level simulation on a desktop computer. This could potentially be "running linux" at a reasonable (if sluggish) speed.

Re:The “high-level CPU” challenge (2008) by adwn on Tuesday February 28, 2017 @12:53AM (#13751587)
> Unless you're NVIDIA, Intel, AMD, or Qualcomm, Apple, Samsung (you get the idea) why would you ever want to build anything besides "small and/or highly regular chips"?

What's your point? The ASIC emulation market exists, there are several companies that build and sell ASIC emulators, and Xilinx and Altera cater to that market with dedicated FPGA devices. I'm not sure why you're arguing here.

Re:The “high-level CPU” challenge (2008) by vmsplice on Monday February 27, 2017 @05:34AM (#13743256)
I'm just a curious hardware development newbie passing by but would you be willing to share the open-source development tools used? It would be really interesting to take a peek at something that was used to develop a chip very quickly. Most of the hardware stuff seems to be quite complicated and not all that open.
Re:The “high-level CPU” challenge (2008) by rwmj on Monday February 27, 2017 @09:03AM (#13744195)
I'm not the original poster, but perhaps he's thinking of https://chisel.eecs.berkeley.edu/ I believe it can (or could?) generate C++ code which compiles into a program that simulates your design.
Re:The “high-level CPU” challenge (2008) by dnautics on Monday February 27, 2017 @01:32PM (#13746554)
They wanted to use chisel for the whole stack, but that was impossible because of one of their engineers.
Re:The “high-level CPU” challenge (2008) by dnautics on Monday February 27, 2017 @01:34PM (#13746570)
Check out verilator