Asynchronous design is a huge sell; we scaled it back to just applying some async techniques to the clock tree of synchronous designs for moderate performance/power improvements.
There are three problems we found:
- the existing toolchain is synchronous-orientated, so you'd have to replace all of it and retrain your staff.
- the chip developers and their managers tend to be older and more conservative than the software world. They're also potentially large teams (Intel are obviously huge). So the retraining is going to be difficult and expensive.
- it's risky. New toolchain and newly trained staff? There's going to be bugs in the tools and errors in the design. Worse, there will be new types of bug that people aren't good at diagnosing. These will take weeks to resolve and a couple of wafer sets. That's a very expensive proposition!
If async is to get a foothold it would be, like ARM, starting at the low end. Low power consumption is an obvious pitch for microcontrollers, and the simpler designs will be less risky.
Given that the answer to that question for the AMULET was 'Errm...', they'd then just abandon it as a processor candidate as being conceptually too difficult to think about.
I wonder if the design could be reworked into Verilog or VHDL and used as an FPGA soft core?
I can't see anything about RISC-V (or any ISA!) that makes a difference to those four points.
Tool complexity isn't really to do with size or complexity of design, although size affects runtime. It's a question of how accurate the physical modelling is and how well manufacturers trust an OK from the tools. And whether the engineers trust the tools and can use them effectively.
There aren't all that many design tool companies, too. Remember I worked for one. The Cadence/Synopsys duopoly is quite strong for the usual reasons.
Fundamentally what you're asking is for someone to make a quarter-million-dollar+ bet on async. It's easy to say "sure it'll be great" when it's not your money.
(Maybe the easy way to do it is to build an app for sending "yo!" to your friends, raise the $1.5m VC, and spend it on silicon instead...)
(Less snarky edit: you know that async isn't a magic dust to apply to existing designs, and that someone would have to write an entirely new core targeting RISC-V in an async style?)
I have no doubt that will eventually happen. There are lots of RISC-V designs already and more underway. If async is really a win, someone wanting to prove that will do a RISC-V chip with it.
The cores themselves are asynchronous, with all of the benefits of lower power. The memories sitting outside of the cores are clocked, however.
I remember being a little bit disturbed by the temperature dependence of the chip on wall-clock execution time but it didn't affect our applications.
It was interesting to find this stuff as a product-ready platform.