It's a very simple instruction set. Whatever the challenges are with asyc design and verification, the task will be simplified with a smaller/simpler processor design. The open source nature of it also means any company or researcher is free to do what they want with it. Design tool companies for example could create that alternative workflow for async and promote it by saying "look at the results we got on RISC-V" and make all the comparisons they want. They could also release the design if they wanted. It's hard to see any of that happening with something like ARM or x86.

Smaller ARM is quite simple, and as mentioned upthread there was already an async ARM - AMULET.

Tool complexity isn't really to do with size or complexity of design, although size affects runtime. It's a question of how accurate the physical modelling is and how well manufacturers trust an OK from the tools. And whether the engineers trust the tools and can use them effectively.

There aren't all that many design tool companies, too. Remember I worked for one. The Cadence/Synopsys duopoly is quite strong for the usual reasons.

Fundamentally what you're asking is for someone to make a quarter-million-dollar+ bet on async. It's easy to say "sure it'll be great" when it's not your money.

(Maybe the easy way to do it is to build an app for sending "yo!" to your friends, raise the $1.5m VC, and spend it on silicon instead...)

(Less snarky edit: you know that async isn't a magic dust to apply to existing designs, and that someone would have to write an entirely new core targeting RISC-V in an async style?)

>> Less snarky edit: you know that async isn't a magic dust to apply to existing designs, and that someone would have to write an entirely new core targeting RISC-V in an async style?

I have no doubt that will eventually happen. There are lots of RISC-V designs already and more underway. If async is really a win, someone wanting to prove that will do a RISC-V chip with it.