I suspect they didn't want to devote lots of die space to SRAM on an early version of the device.

And I'd expect a micro controller to have on-board flash, not some SPI nonsense that has to rely on the 16K cache for performance.

But AFAICT flash memory is an area full of patents and secret sauce. I'm not sure what's involved but it would be nice if some open flash designs become available soon.

SiFive have opened up all the digital pieces of the design (namely HDL and SW), but a lot more is needed to make an IC. Analog I/O, power supplies, clocks, PLLs to name but a few.

Currently "open source IC's" extend to the HDL piece only - embedded flash in 130nm is a highly complicated piece of IP and is either available by third party or through the foundry under license. I am assuming the SRAM physical IP (16KB) in this chip is also a propriety library as well.

Having recently been through building a not dissimilar IC I rushed to be first in line to pick up one of the founders HiFive1 boards (its a great board - really tidy) - this project is a huge step in the right direction. Consider this alternative - in trying to figure out some complicated ARM Cortex-M bug recently, the final solution was found by 'a friend sourcing some information from China'; this is for IP that we'd paid for (although not enough!). ARM are not bad at support at all, but we are very small and help doesn't often come to those who need it in this situations, but those who find it. I'd much rather have an IC with all the digital pieces available and an open community of people integrating it into various projects when trying to make my own project succeed.

It's open source logic design, not semiconductor process. The SRAM for memory and caches is almost certainly fab-supplied too, as are the specific gate layouts, PLLs, etc... All that stuff is going to be secret sauce NDA'd IP specific to the process they were using (FWIW: does anyone know what/whose process that is?). Flash isn't fundamentally any different.

Presumably they just didn't want to devote engineering time to something nonessential for the first project.

Really Flash is more worse than memory, caches, standard cells, PLLs, etc -- it requires significant process additions to fabricate the floating gate, as well as modifications to support high voltages, circuits for high voltage (charge pumps).

The FE310-G000 is TSMC CL018G 180nm

Cool thanks. In which case I wonder if flash is even available on that process. Were 180nm parts doing mixed flash and logic ever?

The well-known PIC16C84 microcontroller was introduced in 1993 and included 1K of 14bit EEPROM code memory. I don't know how difficult it would be to include EEPROM in the FE310, but any 1993 patents have already expired, and even small EEPROM is very useful in many cases because it avoids the need for external memory. If Flash can't be included in an open design then EEPROM would be better than nothing.

Flash surely could be included. But this is HiFive's minimum viable product. Their core deliverable was the CPU core. Peripherals probably got trimmed if they weren't easy.

Quad SPI XIP is pretty common these days. Plenty of modern MCUs bundle it as an option, some like this one (but also some Toshiba part, to name one) use it as the only option. It's workable, and you can put performance-critical code in RAM anyways. That is, if you have enough RAM...

How hard is it getting a risc-v toolchain going for it?