Why hardware development is hard, part 1: Verilog is weird (2013)

Re:Why hardware development is hard, part 1: Verilog is weir... by blackguardx on Thursday November 03, 2016 @12:33PM (#12865454)

To look at it another way, what does one gain? Hardware is highly parallelizable and HDLs give you that capability by default. Verilog is a really easy language to learn. The hard part is learning how to do hardware design.

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Re:Why hardware development is hard, part 1: Verilog is weir... by noescape on Thursday November 03, 2016 @12:50PM (#12865650)

One gains not needing to learn another language. I know C, I don't know Verilog or VHDL. I know how to debug C, I don't know how to debug Verilog.

If I can write a working C program, why can't I make working hardware?

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Re:Why hardware development is hard, part 1: Verilog is weir... by blackguardx on Thursday November 03, 2016 @12:53PM (#12865674)

Knowing how to debug C won't help you. There is no state machine running your code. Stepping through instructions doesn't apply.

Debugging HDL involves looking at timing waveforms in a simulator.

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Re:Why hardware development is hard, part 1: Verilog is weir... by noescape on Friday November 04, 2016 @06:36AM (#12871543)

Could one write a state machine running the code? VMs do.

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