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A comment on Why hardware development is hard, part 1: Verilog is weird (2013). Parent comment

Re:Why hardware development is hard, part 1: Verilog is weir... by blackguardx on Thursday November 03, 2016 @12:53PM (#12865674)
Knowing how to debug C won't help you. There is no state machine running your code. Stepping through instructions doesn't apply.

Debugging HDL involves looking at timing waveforms in a simulator.

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Re:Why hardware development is hard, part 1: Verilog is weir... by noescape on Friday November 04, 2016 @06:36AM (#12871543)
Could one write a state machine running the code? VMs do.
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