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Re:Epiphany-V: A 1024-core 64-bit RISC processor by rthille on Wednesday October 05, 2016 @02:11PM (#12646287)
As I understand it: If memory is coherent then all cores see the same values when they read the same location at the same time. Stated another way, the result of a write to a location by one core is available in the next instant to all other cores, or they block waiting for the new value.
Re:Epiphany-V: A 1024-core 64-bit RISC processor by tomcam on Thursday October 06, 2016 @02:34AM (#12650632)
Thank you all for that help. Did not see definitions elsewhere in post.