Re:A tale of an impossible bug: big.LITTLE and caching
by mayank10j on Monday September 12, 2016 @03:18PM
(#12482788)
what's the incentive for cpu manufacturer to make effort of building extra cache memory in hardware for bigger cpu in ARM64, if there is no sane way to use it ?
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Re:A tale of an impossible bug: big.LITTLE and caching
by pm215 on Monday September 12, 2016 @03:35PM
(#12482920)
This setting is the cache line size, not the total cache size. You can happily give the bigger cpu more total cache.
Re:A tale of an impossible bug: big.LITTLE and caching
by colejohnson66 on Tuesday September 13, 2016 @02:58AM
(#12486107)
The difference between cache line size and cache size is like paper. You can make it wider (bigger cache line size), taller (bigger cache size), or both.
The problem is like printing. If you put in an A4 or letter (ANSI A) sized sheet and tell your printer it's A3 or tabloid (ANSI B), you're gonna have problems.