I keep telling OSS HW people to build on OpenSPARC given you have an ASIC-proven, badass design to start with. Good to see that they not only did that but put 25 cores on a 32nm node. We have Raptor trying to get OpenPOWER for a more open processor, RISC-V designs in the making for multi-core, and the RTL of a fully-open SPARC with 25-cores ready to go. We also have a need for high-performance, multi-core CPU's as our root of trust. Anyone see opportunity? ;)

Next step for any academics reading is modifying these suckers to have extensions like Watchdog[Lite] or CHERI CPU's. Dover is already doing SAFE with RISC-V. FreeBSD already runs on CHERI, though, so hardest work is done. Modify OpenSPARC & compiler backend for it as they did their BERI MIPS. Add I/O MMU & trusted bootloader. Boom! The beginning of a secure, open SOC. :)

It's always cool when research projects show that they would work in the real world. Lots of times they are some professors pet idea and don't really go anywhere. It will be interesting to see if in a year to 18 months if anyone else is using OpenPiton.

Eh, Wentzlaff (professor behind this) co-founded Tilera. He can definitely make something others could use. I view him doing OpenPiton as an attempt to give back to researchers now that he has become a prof.

Why not OpenSPARC T2 ?

I think it's because of these guys' strong focus on FPGAs. If you dig back on the opensparc scene a few years back, you'd find almost no materials on the T2 implemented in FPGA...

Yeah, I see some T1 related academic papers. Research on RISC-V [0] with this hyper-scale architecture would have been a better choice for PI.

[0] https://riscv.org/

I can think of a lot of exciting custom silicon, so if as an Academic you get the extremely rare occasion that someone funds you a 32nm chip... why on earth would you then go and build something that all of the commercial players are also doing?

I suspect the grant was to build this chip rather than to go and have fun play times with a 32nm fab.