Thanks! Actually, doing 4 layers first really helped me save cost on the first prototypes while still allowing me to verify almost the complete design. But that's a difficult question. I think it's inevitable for some things to slip through like they did (the wrong valued resistors...) and 3 revisions to get it right were not that many. One thing I'd certainly do is starting with the FPGA design early on, so I'd not just blindly pick a part that looked suitable like I did this time. That would have also eliminated the mistake where I didn't route clocks to clock capable pins.