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Re:STOKE – a stochastic optimizer for x86_64 assembly by RossBencina on Wednesday January 27, 2016 @04:23AM (#10979099)
I've finished reading the links. The first one was great. Thanks, I learnt something. It's not my field, but I'm vaguely familiar with the workflow, having friends who design ASICs, work at Xilinx, etc. I've encountered some algorithms in advanced compiler texts.

But what I was specifically curious about was applications of stochastic optimization to EDA workflow. It sounded like you'd seen papers on that topic.

My interest is purely in applications of stochastic optimization. I'm not about to jump into EDA.

Re:STOKE – a stochastic optimizer for x86_64 assembly by nickpsecurity on Thursday January 28, 2016 @08:00PM (#10992759)
Ok, now that I know your focus, I basically just used my fast googling technique and searched through recent archives to see if anything popped up. Here's various things in hardware, software, and architecture benefiting from SO to learn from or improve on in your own work.

Really detailed write-up of how cells can be modeled and transformed with stochastic tie in http://www.eecs.berkeley.edu/~keutzer/classes/244fa2004/pdf/...

Parallel, stochastic, FGPA placement with great speedup http://www.eecg.utoronto.ca/~vaughn/papers/fccm2014_parallel...

Multi-optimization scheme for nanometer https://repositories.lib.utexas.edu/handle/2152/3688

Note: This does not do stochastic I don't think but a number of other methods. It's significant because it specifically mentions modern, typically large, designs avoid stochastic optimization for global issues because it's cost-prohibitive compared to geometric methods. That might have significant implications outside EDA, too. Might only be good for local optimizations that are tied together some other way.

Synthesis and control of system design for industrial project (software) http://www.scielo.org.ar/pdf/laar/v40n2/v40n2a07.pdf

RTL verification by minimizing multiway decision graphs (2006) http://citeseerx.ist.psu.edu/viewdoc/download;jsessionid=D9E...

Use in clock-tree synthesis for multi-FPGA's with focus on thermal properties http://thescipub.com/PDF/ajassp.2013.1604.1615.pdf

Synthesis of high-performance analog circuits (1996) https://users.ece.cmu.edu/~rutenbar/pdf/rutenbar-aotcad96.pd...

System levle hardware and software partitioning with simulated annealing and tabu search http://www.gstitt.ece.ufl.edu/courses/fall08/eel4930_5934/re...

Simulated annealing for aiding genetic algorithms in software architecture synthesis http://www.sis.uta.fi/~tp54752/pub/sa/SA_aiding_GA_acta.pdf

Synthesize implementations of hard real-time stuff http://link.springer.com/article/10.1007/BF00872288?no-acces...

Humie awards from Genetic Programming. Most of these could probably be ported to Stochastic Optimization in general. http://www.genetic-programming.org/combined.html

Accelerate floating point problems https://web.stanford.edu/~sharmar/pubs/fp.pdf

Stochastic super-optimization of loop-free binaries https://web.stanford.edu/~sharmar/pubs/asplos291-schkufza.pd...

Note: I'm keeping that one for sure. :)