Re:Why I will be using RISC-V in my next chip
by wmf on Saturday January 09, 2016 @08:55PM
(#10873776)
The point of VLIW is to eliminate the hazard detection and scheduling logic required by normal superscalar, but SMT would require much of that logic to be added back. So VLIW can't really use SMT. VLIW could use FGMT (e.g. barrel processor) or SoEMT, but those can't fill the empty issue slots caused by bad instruction mix.
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