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A comment on Why I will be using RISC-V in my next chip. Parent comment

Re:Why I will be using RISC-V in my next chip by zhemao on Saturday January 09, 2016 @07:40PM (#10873574)
We already have a RISC-V superscalar out-of-order core, the Berkeley Out-of-Order Machine (BOOM).

https://github.com/ucb-bar/riscv-boom

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