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A comment on Why I will be using RISC-V in my next chip. Parent comment

Re:Why I will be using RISC-V in my next chip by legulere on Saturday January 09, 2016 @07:19PM (#10873515)
By what I've been told, VLIW makes only really sense in some use cases such as DSP processors. With general purpose computing it happens way too often that you can't find enough instructions that are independent of each other. For the case where it is possible to execute instructions in parallel, you can make your CPU superscalar. The simple nature of the RISC-V ISA probably should make supercalarability easy and performant.
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Re:Why I will be using RISC-V in my next chip by zhemao on Saturday January 09, 2016 @07:40PM (#10873574)
We already have a RISC-V superscalar out-of-order core, the Berkeley Out-of-Order Machine (BOOM).

https://github.com/ucb-bar/riscv-boom

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