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Re:Nibbler 4 Bit CPU by duskwuff on Tuesday October 13, 2015 @01:52PM (#10382157)
> You're forgetting the memory elements – they're crucial to the functionality of FPGAs.

I'd argue that an even more critical feature of FPGAs is configurable routing. ROMs don't have that either. :)

Re:Nibbler 4 Bit CPU by adwn on Tuesday October 13, 2015 @03:02PM (#10382685)
True. But then again, that's like arguing over which organ is more important – the heart or the lung – when you can't survive without either of them ;-)
Re:Nibbler 4 Bit CPU by duskwuff on Tuesday October 13, 2015 @11:16PM (#10384806)
You can build memory elements - inefficiently, but it's possible - out of recurrent logic. You can't build routing.

Actually, now I wonder whether it'd be possible to build memory out of ROM by looping outputs back to inputs...

Re:Nibbler 4 Bit CPU by adwn on Wednesday October 14, 2015 @02:57AM (#10385338)
> You can't build routing.

You actually don't need configurable (programmable) routing: We can model every synchronous circuit as a Mealy machine [1], therefore we need two functions and a register. Every function can be constructed from a hierarchy of programmable, fixed-size LUTs which are statically connected (for example, you can build a 5-input LUT from three 4-input LUTs). Now you don't need to build routing, it's implicit in the next-state and output functions.

[1] like this: http://electrosofts.com/verilog/mealy.gif