PicoRV32 – A Size-Optimized RISC-V CPU

Re:PicoRV32 – A Size-Optimized RISC-V CPU by pdq on Tuesday September 22, 2015 @01:09PM (#10259993)

Note this is the same Clifford Wolf who has built a Verilog synthesizer [1] and reverse engineered the Lattice FPGA bitstream format [2].

On a slightly different topic, the RISC-V group has built an impressive Javascript RISC-V emulator that boots Linux in your browser: http://riscv.org/angel/

[1] https://github.com/cliffordwolf/yosys

[2] http://www.clifford.at/icestorm/

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Re:PicoRV32 – A Size-Optimized RISC-V CPU by tkinom on Tuesday September 22, 2015 @02:04PM (#10260388)

Very nice!

Boot http://riscv.org/angel/ into linux busybox in the browser

/ # cat /proc/cpuinfo

CPU info: PUNT!

/ #

What does "PUNT!" mean?

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Re:PicoRV32 – A Size-Optimized RISC-V CPU by duskwuff on Tuesday September 22, 2015 @02:54PM (#10260777)

It means that the RISC-V Linux port hasn't decided what to put in /proc/cpuinfo yet. The contents of that file are not standardized across architectures, and indeed there isn't much meaningful information to provide there on certain CPUs.

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Re:PicoRV32 – A Size-Optimized RISC-V CPU by monocasa on Tuesday September 22, 2015 @02:35PM (#10260632)

It means that there's still work to do on the Linux port and RISC-Vs supervisor mode ISA in general.

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Re:PicoRV32 – A Size-Optimized RISC-V CPU by ant6n on Tuesday September 22, 2015 @08:52PM (#10262720)

There's an OpenRisc in-browser emulator which seems to give you a more functional linux:

http://s-macke.github.io/jor1k

The cpu in /proc/cpuinfo is OpenRISC-12 @ 20MHz ;)

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