PicoRV32 – A Size-Optimized RISC-V CPU

Re:PicoRV32 – A Size-Optimized RISC-V CPU by krupan on Tuesday September 22, 2015 @12:55PM (#10259869)

This repo appears to include scripts to build this for a Xilinx 7 series FGPA. So once you buy a dev board with an Artix 7 (a quick google search shows it's about $400) and install the Xilinx tools (should be free) you can just type make and it will build the bitstream that you can load onto the FPGA.

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Re:PicoRV32 – A Size-Optimized RISC-V CPU by rjsw on Tuesday September 22, 2015 @01:15PM (#10260043)

A Parallella board is a fair bit less than $400, the Zynq is 7 series too, the scripts would need modifying a bit though.

The larger Rocket RISC-V implementation will also run on a Xilinx Zynq.

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Re:PicoRV32 – A Size-Optimized RISC-V CPU by zhemao on Tuesday September 22, 2015 @02:37PM (#10260643)

Here at Berkeley, we've successfully run our RV32I processor, Zscale, on an $89 lx9 microboard. But this took some hacking of the FPGA support repo, so it isn't officially supported.

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