throwaway000002
throwaway000002 on Hacker News
Because we all know AAPL takes its proportional percentage of flesh from an app developer for having the audacity to add value to iOS, whilst simultaneously holding back the web.
Hypocrisy all around.
I'm not, however, going to comment on any other part of your response. I just don't want to get into it.
Sure, I mostly feel like an ungrateful wretch. And yes, now that he's an old man, I do treat him very poorly and wish he were dead, mainly because it'd save my feelings of guilt with how I treat him.
I wonder if he resents having me. I will never ask him. I fear his reponse, that he'll deny it.
If you're willing to have a kid, I'm one of the ugly corner cases.
I don't have any kids. I'm beyond the age where they're on my radar. Perhaps a relationship with someone a fair bit younger would change that, but I doubt it.
Good luck.
Why registers? I haven't studied the Tomasulo algorithm in any detail, but if you're going to do "register renaming", why have registers at all? You could, for example, treat memory as a if-needed-only backing store, and then add a "commit" instruction that commits memory (takes an address, or a range). Sure you need to make changes with how you do mm i/o and protection, but at a basic level: why registers?
I'm glad FPGA's are becoming a thing, and I think we're about a decade or two away from ASICs as a service, because if you're not beholden to tradition, you really can work some magic. Of course I'll be pretty rusty by then, but who knows, maybe medicine will keep me feisty.
I'm also the weirdo that feels process isolation, memory management, and I/O mechanisms need a rethink. But that's something that would take me forever to get into.
One thing I will say, though, is alignment issues "infect" everything. Assume your architecture doesn't allow misaligned access. Now, all your data has to be naturally aligned. Your structs now have to be aligned to the alignment of the largest sub-structure within them. This is all because code is alignment sensitive. Given a pointer to a struct, generic code is unnecessarily larger. Any why would we care? Communication, of course. If we're exchanging data between systems then idiosyncrasies such as this suddenly become globally visible.
Endian-ness must be little. Byte-aligment a non-issue, and network-bit order should be from bit zero up, with any upper layer need, say for cut-through forwarding, expressed as a data ordering requirement, so for example an IP4 address is not a blind 32-bit word, but specifies the structure of those 32-bits.
Which brings me to padding. I wonder what percentage of memory of the average 64-bit user's system is padding? I'm afraid of the answer. The heroes of yesteryear could've coded miracles in the ignored spaces in our data.
Libralato (gasoline) engine technology
Keeping the faith alive...
1) It's still impossible for anyone to get their hands on an FE310 chip over half-a-year on from the release of the HiFive board.
2) They promised open-source cores, but somehow backtracked due to "customer requests". How does this make any sense? And if so, just have an open-source version, and a closed-source one that, I dunno, has a SiFive logo on the mask.
I was really inspired by them, now I'm mostly dejected. Still, I'm hoping someone like ST takes their peripherals and makes an MCU with a RISC-V.
Intel Quark S1000 “Sue Creek” Processor to Support On-Chip Speech Recognition
Counting Down to the New Ampere (2016)
Terabit DSL [pdf]
RISC-V User ISA v2.2, and Privileged Architecture v1.10
GAP8 IoT Processor
RISC-V cores get support, fees
SiFive launches RISC-V processors, reveals pricing
SiFive Coreplex RISC-V IP
I saw the slides on the VM threads concept. I'm unsure as to the point. A process essentially sees a virtual CPU, multiplexed by a kernel. The point of a hypervisor could be understood as multiplexing things (aka OSes) that weren't written to share hardware.
What exactly is the point of a VM thread, which I understand as something which makes a VM look to a kernel as a process?
There doesn't seem to be any "win". Apart from perhaps making implementing Type II hypervisors, like KVM, easier. My critique of them is that their TCB is far larger than the Type I kind.
And all this for an architecture that doesn't have any legacy binary software... very strange.
He then adds, "But there's also credit due to the many thousands of people here who have figured out how to turn trash like this [shows mangled screen assembly] back into beautiful working phones."
Dear friends in Shenzhen, not all Westerner's are as shallow and fantastically, well, douchey as this asshole. We praise you for your ingenuity and unwavering work ethic. Thank you.
But in light of this, I see him as essentially correct. Any one of them could demand payment from ISPs for their content (their endusers would revolt otherwise). The new willingness to dismantle "net neutrality" does not hurt any of them, only startups. And, as for the carriers, cablecos, telcos, etc, their window of monopoly is over, they should have invested in content when they had the chance.
Intel to mislead press on Xpoint next week
“Toyota's Killer Firmware” and the “Single Bit Flip That Killed”? Not
I don't need, nor want, anything else.
Also, get off my lawn.