sybreon

I think that the context matters. In the case of an external consultant being asked to sign an NDA (whether prematurely or otherwise), Eric S Raymond presents some compelling arguments on why and how NOT to sign them. http://esr.ibiblio.org/?p=2394

Hardware implementation in synthesisable Verilog RTL.

Synthesises to about 700+ slices at 150MHz on a Spartan6.

https://github.com/sybreon/dcpu16

Done! http://sybreon.github.com/dcpu16/

Multi-cycle operations can actually be inserted into the pipeline. The `ena` signal would just need to be held low during that time.

Already done. https://github.com/sybreon/dcpu16

There's already one! https://github.com/sybreon/dcpu16

The core is written entirely in synthesisable Verilog RTL. Synthesises to about 700+ Slices at around 150MHz on a Spartan6. (minus h/w division and modulo)

Feel free to extend/expand/contribute.

I posted it on HN yesterday. http://news.ycombinator.com/item?id=3821400

I started with LOGO in 1989 and BASIC in 1992. So, 20-odd years or so. And still at it!

Though, I've got a lot less time to focus on it now, with all sorts of other worldly responsibilities.

We do? o_O

Kuala Lumpur, Malaysia.

Aeste - http://www.aeste.my/hiringnow

Swimming (and drowning) at the software-hardware boundary.

We are currently looking to fill several full-time engineering positions.

If you are looking for a place to experience an alternate work culture within Malaysia, feel free to apply. At AESTE, you will be given the opportunity to impact the world in unexpected ways.

From the mathematician on stage: "and for some reason, Sony uses the same random number all the time!" - classic!

You DO NOT have plenty of time! Kids grow up so quickly that before you know it, he'll be 18!

Kuala Lumpur, Malaysia.

Work involves swimming and drowning at the software-hardware interface. Home of the smallest and fastest 32-bit multi-threaded embedded microprocessor core.

http://www.aeste.my/internships

An alternative:

Install a proxy server, such as squid, on your local machine. Point your browser to use the local proxy server. Some stuff will get cached on your proxy server and will not be loaded from the Internet.

You can install some additional filters and chain your proxy servers so that they strip out adverts and what nots.

Does anyone know the name of the new theme and if it is available for download on the site?

Yup, but foreigners get a choice of whether or not to contribute.

Kuala Lumpur, Malaysia

I assume that this is for an entry-level position.

Monthly salary : ~ US$650-$950 (Average US$800).

EPF deduction: 11% Room Rent: US$150. Food: US$250 (3 ramen sized meals) Car Installment: US$100 (Perodua Viva) Petrol: US$50

These are the costs for survival mode living.

Optional Movie ticket: US$3-5 Internet (1Mbps): US$35 Mobile (300 mins): US$10 Alcohol: Forget it.

Kuala Lumpur, Malaysia - Aeste (http://www.aeste.my/careers).

Swimming (and possibly drowning) at the software-hardware interface. Projects will largely involve building an ecosystem around the world's smallest and fastest 32-bit multi-threaded microprocessor core.

With a web-app like this, I would be concerned about IP issues. Half the industry is banking on IP unless they are open-source like the OR1K. Otherwise, a proprietary house might be hesitant to upload HDL code even if it is over a secure SSL connection.

For simulation with Icarus Verilog, it might be possible to upload the compiled VVP binary. You can sell your computing power as a utility (ala cloud computing) and help people save cost from buying an expensive server and save time from having to wait days for results.

For FPGA selection, I personally doubt that your tool would be that useful because this decision is primarily dictated by the cost of parts - rather than the specific features. The hardware business is very cost-driven. What you can do is to provide customers with the ability to perform synthesis over multiple architectures for the purpose of 'testing' that their code works on them all.

Measuring the relative power draw due to flipping logic can definitely be done with present day simulation tools. The question is whether there is any significant advantage in saving X% of power in the processor core. In a complex system, the processor rarely sucks up most of the power. Someone should actually do this as a research and find out if there are any significant savings.

I am guessing that it will all be architecturally specific. An ARM will have a different power profile to a MIPS running the same C code. Personally, I would like to see the option of a -Op switch to GCC that selects power-optimised code paths.

Not in the similar vein, but I would recommend "The Last Lecture" (by Randy Pausch). It was very inspirational to me. http://www.amazon.com/Last-Lecture-Randy-Pausch/dp/140132325...

Try sheet music?

Writing a synthesis tool is like writing a high-level language compiler, fairly difficult. On top of that, synthesis (by definition) targets a specific technology. This is like targeting different CPU architectures and platforms with said compiler except that the targets are not publicly documented.

Even with so many OSS developers in this world, we only have one decent compiler that targets multiple platforms - GCC, and even that has lots of issues. The number of FPGA developers is far smaller and most of us would rather focus on the hardware design, than write software tools.

So, if you want to see a good FPGA tool chain, you would need to convince enough FPGA developers with software skills and enough software developers with hardware skills, to put an effort behind actually making it work.