spaintech
For some critical software we developed, we used TLA+ for high-level formal specification. As mentioned earlier, transitioning the actual implementation to another language can be challenging, especially if partial hardware bootstrapping is required. We ended up implementing the high-level specification created in TLA+ using ADA/Spark, which minimized our exposure to buffer and assertion failures. However, optimizing the code to meet performance thresholds was at times frustrating and time-consuming, like any low-level implementation with a new tool/language for us.
I’m curious about any new tools or workflows for leveraging TLA+ high-level specification implementation into other languages like C and Rust. What approaches are people taking once the formalized specification is verified in TLA+ to complete the implementation?
I might be out of the loop, but using TLA+ spec and translate then to other languages hasn’t been a successful use case for LLMs. While they can be helpful, a significant effort is still required to ensure that implementations accurately adhere to the specifications.
Current ISAs have so much machinery underneath that it’s hard to tell when you’re talking to the iron and when you’re talking to the microcode
You can still argue that Forth on a Forth CPU is a genuinely low-level language. :)
For frontier labs, their fund-train-new model play might not be as effective, and a shift of spent of compute cost moving away from training to inference might be a tell-tell sign of the LLM as we know it plateauing out as scale is just not as effective. Open models might also be placing a major pressure on meeting then revenue targets need to sustain the model, lots of customer hosting their own inference to mitigate costs.
If you only move the needle just slightly in the direction of inference, frontier labs will soon loose their alphas. Becoming just another SaaS for inference might not be as attractive unless you are Google/MSF ( IMHO ).
Should this pan out, it could be a scenario where the NeoClouds could soon loose their biggest customers, so I tend to agree with that aspect of Zitron’s view.
Thoughts?
Tethered Forth programming on small devices is an underrated opportunity, IMO. There is also the opportunity to revise the OpenBoot project, I remember the days of automation for deployments at the Bios, it was an amazing tool for massive deployments of Sun T systems in telcos.
Is it feasible to exploit these undocumented HCI commands to develop malicious firmware for the ESP32? Such firmware could potentially be designed to respond to over-the-air (OTA) signals, activating these hidden commands to perform unauthorized actions like memory manipulation or device impersonation.
However, considering that deploying malicious firmware already implies a significant level of system compromise, how does this scenario differ from traditional malware attacks targeting x86 architectures to gain low-level access to servers?
In other words, language models are advanced pattern recognizers that mimic logical reasoning without genuinely understanding the underlying logic.
We might need to shift our focus on the training phase for better performance?
Comparing cooperative geometric puzzle solving in ants versus humans
They way I’m considering this is, one could provide virtual time sources, removing the high resolution timers, where the OS has more of a coarse-grained timer. Not sure the implications, but if needed, one could add jitter or randomness ( Noise ) to the virtual timer values…
This would further prevent thread from running out of sync with the resto of the threads.
Further, one could also add a stack based shared memory model, LIFO would provide a highly predictable behavior from an application perspective. If you make it per process, the shared stack would then be confined to the application. No sure if possible ( haven given deep thought ) but the stacks could be confined to specific cache lines, removing the timing differences caused by cache contention…
Wondering if a well defined OS system, with strict enforcement of memory boundaries at the OS level and at the application level, where the application sits in a well defined deterministic execution model would mitigate some of these unpredictable state transitions.
If one considers a minimalist OS, micro kernel for example, lowering the attack surface, would this not explicitly prevent access to certain microarchitectural states (e.g., by disallowing certain instructions like clflush or speculative paths)? This could be accomplished with a strict memory management jointly at the OS layer and the binary structure of the application… one where the binary has a well defined memory memory boundary. The OS just ensures it is kept with in these limits.
Applying this to Starlink, its emergence as a leading provider in satellite-based mobile connectivity could be seen as a result of substantial innovation and investment. Such a position enables the company to offer services that were previously unavailable or limited, particularly in underserved regions. Considering Milei’s argument suggests that in the absence of government-imposed barriers, a monopoly like Starlink’s can maintain competitive pricing to deter potential competitors, ensuring consumers benefit from both advanced technology and reasonable costs.
Milei emphasizes that market failures are often the result of state intervention rather than the natural outcome of market dynamics. In the case of Starlink, minimal regulatory interference could allow the company to operate efficiently, maintaining an environment where innovation thrives, and consumers receive enhanced services. Its the potential drive of the market (competitors) and innovation to keeps them in check with pricing and perceived consumer value. [2] [3]
[1] https://www.hoover.org/news/market-ourselves-argentine-presi...
[2] https://www.weforum.org/stories/2024/01/special-address-by-j...
The Forthic repository on GitHub offers two primary interpreters:
1. Python-based Interpreter: Designed to run within a Flask application, enabling the creation of APIs that can be revised at runtime.
2. React-based Interpreter: Facilitates the creation of user interfaces on-the-fly.
For a comprehensive overview of Forthic, see: https://github.com/linkedin/forthic
Forth on top of Python-React makes for Forthic: a showcase of Forth productivity [video]
Well, IMHO, when considering a project, knowing that you are solving for a customer demand problem is very different than from a VC minded problem. I personally would never advise or be part of such an “Arrangement.” These are my clear principles, and my success will come or fail, but my integrity will never be questioned.
I find it both interesting and exciting to see a new os for the could era. I do feel like the DBOS is still not singular, PICK ( already mentioned) but also mentioned in other thread where Taurus OS and the Plant 9 project, which also leverages a database on a file system as a core for system resource management.
In my own thinking of a cloud OS, and particularly considering the focus on server-less applications as mentioned in the article, I have been inspired by Forth’s Dictionary data structure as a lightweight data structure concept where the core state and application contexts are managed through modular dictionaries, each with isolated and secure contexts. OS has a Core Dictiory, and each application is contained with in it’s own namespace dictionary… ect.
Message passing between applications could be efficiently handled using a tagging/queue system, potentially extending to RDMA for distributed environments. This could offer a lightweight, performance-optimized alternative current OS options, particularly in resource-constrained or highly distributed systems for server-less infrastructures.
I'm hopeful that Snapdragon will offer an alternative ARM platform for laptops that can handle more than just browsing. As consumers, we need options, and the more, the merrier. I'm still undecided about the short-term success of Snapdragon. For now, I'm betting/waiting on the MacBook Air with an M4 as my daily driver, although I do prefer the Lenovo ThinkPad format.
I’d like to congratulate the author, this is not only a great source of technical depth in the real of languages, but also a great read as far as the layout and the small details in the graphics made is a source that I just keeps me engaged in the reading. I’s one of those books that feels will be relevant for many-many-years to come!
Congrats and thank you!
I know that it is substantially supported on the ESP32, which is great, but I’m not sure if it’s able to give you the HW access that Forth has, you can extend and build your own drivers on the Forth system, which is my main use case. I like to do things as bare to the metal as possible and C and forth give me that, it’s the same reason I never used the arduino framework.
Your comment “Fantastic, love the writing style and the graphics! Simple, compact, and useful.” reflects an appreciation for the article's clarity and visual appeal. To extend this, you might consider highlighting specific elements that stood out to you. For example:
I particularly admired the way complex technical concepts, like the Platform-Level Interrupt Controller and UART Interrupts, were explained in a straightforward manner.
(I wish I could hand draw that well. :) )
The graphics played a crucial role in demystifying the intricacies of RISC-V Interrupts and the initialization process in the BL808 SoC.
It's impressive how the article managed to make such dense material accessible and engaging, especially the sections on enabling interrupts and handling them through the PLIC.
The troubleshooting part, detailing the unexpected behavior with interrupt priority, was especially useful, I have been bitten by that very essence in UART dev.
I recommend the article, it serves as an excellent resource for anyone delving into RISC-V architecture or embedded systems programming. I think it extends to most UART development actors RISC systems in general. Well done!