sdbbp

Was there a populist (home) mining fad? People got excited about digging for possible resources and dug crude exploratory tunnels?

Try some peñas folklóricas.

The people in that list all sound sketchy. Where are the "good guys"?

That's the HDL, and not the inherent design complexity.

Fediverse: https://mastodon.social/@elonjet

See also https://www.cs.cmu.edu/afs/cs/academic/class/15740-f18/www/p... and Gharachorloo's thesis paper.

Probably "A Primer on Memory Consistency and Cache Coherence"

It would be interesting to see this interact with the lower-level ISA memory model work in diy, litmus, etc. Could you validate your ISA memory models against the generated litmus tests in https://www.cl.cam.ac.uk/~pes20/ppc-supplemental/test6.pdf, https://github.com/litmus-tests/litmus-tests-riscv?

If you like following historical diaries, @samuelpepys is hard to beat.

I used to go to Sundown yearly, a long time ago. I'm not saying it's great, but I did learn to ski there.

https://www.sundownmtn.com/the-mountain/snow-report-trail-ma...

Consider a separate architect to design the place with you. They can help find a general contractor to be the "builder", but also serve as an owner's representative to oversee construction intent. They want the design done well, as well.

This organization of functionality is intentional. It provides support for code modification orthogonal to instruction cache coherency support. The range of types of implementations of RISC-V is broad enough that imposing instruction cache coherency on all of them wouldn't be optimal. The I/D consistency proposal provides SW control now, while not requiring particular implementations.

Particular RISC-V Platform specs may end up requiring I/D coherency, like Arm is recommending in SBSA Level 6, but that's left for later, if ever.

This in-depth presentation is good: https://www.youtube.com/watch?v=oTaOd8qr53U

Ventana Micro Systems | Software Engineer | San Francisco Area, Pune, Bangalore | ONSITE (except COVID-19) REMOTE (US, possible) VISA | Full Time | http://ventanamicro.com

We are a well-funded start-up, founded by seasoned industry veterans, that is developing a family of best-in-class, high-performance RISC-V CPU cores focused on a chiplet form factor. Start working now in the growing community around the open RISC-V instruction set architecture.

Software Engineer: Software development and performance optimization for high-performance embedded and server platforms. Various roles available. Work on compilers, language runtimes, operating system internals (Linux), device drivers, hypervisor, boot and runtime firmware, much of it open source. [email protected]

This was clarified this year. I think the author's context is moving from Bare to one of the Sv modes.

https://github.com/riscv/riscv-isa-manual/commit/866326d938c...

Ventana Micro Systems | Software or Design Verification Engineer | San Francisco Area, Pune, Bangalore | ONSITE (except COVID-19) REMOTE (US, possible) VISA | Full Time | ventanamicro.com

Ventana Micro Systems is a well-funded, early stage start-up, founded by seasoned industry veterans, that is developing a family of best-in-class, high-performance RISC-V CPU cores and compute subsystems. Start working now in the growing community around the open RISC-V instruction set architecture.

Candidates with significant experience in the following areas requested.

Software Engineer: Software development and performance optimization for high-performance embedded and server platforms. Various roles available. Work on language runtimes, operating system internals (Linux), device drivers, hypervisor, boot and runtime firmware. [email protected]

Design Verification Engineer: Functional design verification of CPU cores and related components. Focus on architecture and / or microarchitecture. Infrastructure, testplans, testbenches, test generation, coverage and debug. Simulation and formal. Work primarily in SystemVerilog, Python, C, and assembly. [email protected]

In my experience, writing a formal specification _once_ in TLA+ has shaped my mindset around architecture, implementation, and verification of distributed systems for the last 19 years. It's easier to provide feedback on most informal architecture specifications. It is easier to implement to a specification so as to have a higher confidence of compliance. It is easier to consider the state space of an architecture (distributed system) when in a testing/verification role.

There's little open development, so there's little incentive to write up public articles. You could try something like Bob Colwell's "The Pentium Chronicles".

The amount of effort spent on what is generally called "functional verification" is much higher for hardware than for software. Also, the specifications tend to be clearer and the source code size is smaller than you might imagine.

I use greencine.com

Blame San Mateo County for rejecting BART 50 years ago. http://www.bart.gov/about/history/