random__duck

All while complaining about the OLED price.

Just like Alta Vista and Netscape put there first mover advantage to use?

Even the smallest margin or error in the demand forecast will put them at a huge loss, I can't imagine sleeping well at night if I was on that management team.

Opened the RTL, looked at the floating point math, learned that apparently you don't need correct floating point operations for LLMs, closed the page.

Finally, thanks for stating the obvious! I was starting to wonder if I was not going insane.

A team of senior elite chip designers builds something they already know how to build and everyone goes "wow AI be so powerful".

Open source FPGA silicon in the wild, and it works.

> slighly crazy

What a lovely euphemism.

Signed: someone slightly crazy.

"This time its different".

I wonder if they will be inviting him to the next RISC-V design committee meeting.

Spot on, while reading this post I couldn't help be wonder "but what about the prototypes"?

No AI was used either for the project itself or for the post. I encourage you to look at the code and the git history.

As the designer of "an ethernet connected beacon that counts and never overflows until the heat death of the universe" (https://talesonthewire.com/projects/until_heat_death_do_us_p...) I believe you have found the perfect audience for a memeish hardware project. So don't expect anything but my upmost support. :)

I detailed the roadmap for custom ASIC design a bit here: https://talesonthewire.com/projects/two_weeks_until_tapeout/... and joining the Tiny Tapeout discord community is a great place to reach out for help.

No AI was used either for the project itself or for the post.

Nice, thanks for posting the link. For the people unfamiliar with the Tiny Tapeout program: everyone that gets a copy of the Tiny Tapeout chip will be getting a copy of all the ASICs on the shuttle.

True, I went over the EDA stack a bit in a previous article here: https://talesonthewire.com/projects/blake2s_hashing_accelera...

This used the librelane classic flow, so it's a lot of verilator, yosys, openroad, opensta, magic and klayout. :)

You can join multiple Tiny Tapeout tiles (grid squares) together to form bigger projects, which is what I did here. It's actually one of the bigger 4 grid projects.

Also how much you can fit really depends on the node the shuttle is targeting. So I was in luck that this was on Global Foundries 180nm as you can cram in a lot for flip-flops onto a single tile compared with Skywater 130nm. On the other hand the gates are much slower than on Skywater 130nm.

Hopefully both programs will be around for a while, so if you are still interested when you have more time you can join the shuttle then.

Sounds like they could have used you on that team. Bad luck, but it at least you can walk away proud knowing it was not an issue with your technical skills. :)

Well that isn't good new for google's advertising review if this is a trend.

This is great!

I love this essay so much, it is such on point.

Now this is a future 100 billion dollar industry!

Can I do a "hold my beer" moment ? https://github.com/Essenceia/ethernet_switch_asic

Thanks :) Yeah, the router is defiantly further in the future to, as it additionally requires CPU integration for run the software stack, switches are the first order of business.

Alright I am back from the trenches after having written 1k words and as expected: I did not impress myself.

Haha, nice one. Defiantly all wrong, if hardware design was a religion I might have been excommunicated for this. Deploying the fix now, it should have been "all nighter".

The animated graphics at the end are really cool, how did you make them ?