otherjason

The analogy here is that a lot of consumers recognize those restaurants that are simply reselling pre-made food without much value-add, and choose not to eat there.

Apple events are full of these meaningless statements, which always drive me crazy. Of course it's the "best iPhone Apple has ever made." If it wasn't, then wouldn't I be better off buying an older model?

The cynical way to look at this is that the purpose of the system (the privacy nutrition label) is to support Apple's carefully-crafted and -marketed image as the most privacy-focused of the tech giants. Actually having enforcement of the contents of said labels would be a nice potential byproduct of that, but that's not strictly required to accomplish the system's purpose.

They are probably not going to be implemented using long put positions, but a product with a similar return profile to what you're looking for is a buffered ETF. Basically, over a defined period, you agree to a maximum possible downside in exchange for a capped upside. They are available in ETF form from a number of providers.

For example, you could have an S&P 500 fund that, over the next year, will have a maximum of 0% capital losses (it can't go down), you will only get the first, say, 5% of gains that the equity index makes. So if stocks go up 20% the next year, your return is capped at 5%, but if they crash 50%, you don't absorb any capital losses. In practice, the return cap is going to be just a bit above the corresponding Treasury bill for the same duration.

These can be constructed in various different ways and institutionally I'm sure there are more bespoke ways that are more efficient from a fees/returns and tax perspective, but one way to do this on your own without going the ETF route is:

- Pick an amount you'd like to invest. - Buy a Treasury bill for some duration. Treasury bills are discounted at the time of purchase and return the target amount when the bill matures. For instance, if you buy a $100k 1-year Treasury bill, it might cost $96.5k today. - Now you have $3.5k in your pocket and a guarantee that you'll get $100k in a year when the bill matures. Use that $3.5k now to purchase call options or vertical spreads on the S&P 500 index to capture the upside that you can. Your return is limited by the structure of that options trade and what its maximum payoff is.

If you're willing to accept more than 0% downside, then you can achieve a higher potential upside cap as well.

Indeed, I was referring to the parent comment.

This reads as pretty clearly AI-generated text, which is against HN guidelines.

Almost every Intel CPU released since 2013 has AVX2 support. Some Atom SKUs were longer holdouts, but the fraction of x86 CPUs shipped in the last decade that have AVX2 support is very high.

The statistics reported by GitLab for the x264 repo (https://code.videolan.org/videolan/x264) report that the project is 13.5% assembly; common utilities used in the inner loops of the codec have optimized assembly implementations for several CPU architectures.

See this correct comment above: https://news.ycombinator.com/item?id=47061696

AVX512 leading to thermal throttling is a common myth that from what I can tell traces its origins to a blog post about clock throttling on a particular set of low-TDP SKUs from the first generation of Xeon CPUs that supported it (Skylake-X), released over a decade ago: https://blog.cloudflare.com/on-the-dangers-of-intels-frequen...

The results were debated shortly after that by well-known SIMD authors that were unable to duplicate the results: https://lemire.me/blog/2018/08/25/avx-512-throttling-heavy-i...

In practice, this has not been an issue for a long time, if ever; clock frequency scaling for AVX modes has been continually improved in subsequent Intel CPU generations (and even more so in AMD Zen 4/5 once AVX512 support was added).

The only CPU I've encountered that supports SVE is the Cortex-X925/A725 that is used in the NVIDIA DGX Spark platform. The vector width is still only 128 bits, but you do get access to the other enhancements the SVE instructions give, like predication (one of the most useful features from Intel's AVX512).

What makes you think that RAII- and arena-based strategies are in tension with one another? RAII and smart pointers are more related to the ownership and resource management model. Allocating items in bulk or from arenas is more about where the underlying resources and/or memory come from. These concepts can certainly be used in tandem. What is the substance of the argument that RAII, etc. are "hot garbage?"

The parking spaces in question aren’t free; the city sold the long-term rights to operate the parking facilities to the private sector in a bid to balance one year’s budget.

Overprovisioning is much less aggressive than this in practice. A read-oriented SSD with 15.36 TB of storage typically has 16.384 TiB of flash. The same hardware can be used to implement a 12.8 TB mixed-use SSD (3 DWPD or more).

But, if model development stalls, and everyone else is stalled as well, then what happens to turn the current wildly-unprofitable industry into something that "it makes sense to keep spending billions" on?

I think they were trying to say “radix sort is a more important application of prefix sum than extraction of values from a sparse matrix/vector is.”

Where did you get the pricing for vast.ai here? Looking at their pricing page, I don't see any 8xH200 options for less than $21.65 an hour (and most are more than that).

The last few generations of GPU architectures have been increasingly optimized for massive throughput of low-precision integer arithmetic operations, though, which are not useful for any of those other applications.

This is the common argument from proponents of compiler autovectorization. An example like what you have is very simple, so modern compilers would turn it into SIMD code without a problem.

In practice, though, the cases that compilers can successfully autovectorize are very limited relative to the total problem space that SIMD is solving. Plus, if I rely on that, it leaves me vulnerable to regressions in the compiler vectorizer.

Ultimately for me, I would rather write the implementation myself and know what is being generated versus trying to write high-level code in just the right way to make the compiler generate what I want.

It doesn’t sound like they are referring to newborns needing to be physically present to get a SSN. Instead, it seems to refer to persons who are registering to start receiving their Social Security benefits (or existing recipients who want to change their direct deposit information). Also, there is an existing supported method for identifying yourself electronically that is mentioned in the article. In that sense, the headline seems a bit misleading.

And "our best iPhone ever." If it weren't your best iPhone ever, then I would be better off buying one of your older models.

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If your roboadvisor is buying the individual stocks that make up the index in my personal account for me, do you have data that compares the slippage (bid/ask spread) paid across all of these transactions versus a single purchase of very liquid ETFs like SPY?

For devices with compute capability of 7.0 or greater (anything from the Volta series on), a single thread block can address up to the entire shared memory size of the SM; the 48 kB limit that older hardware had is no more. Most contemporary applications are going to be running on hardware that doesn’t have the shared memory limit you mentioned.

The claim at the end of your post, suggesting that >1 block per SM is always better than 1 block per SM, isn’t strictly true either. In the example you gave, you’re limited to 60 blocks because the thread count of each block is too high. You could, for example, cut the blocks in half to yield 120 blocks. But each block has half as many threads in it, so you don’t automatically get any occupancy benefit by doing so.

When planning out the geometry of a CUDA thread grid, there are inherent tradeoffs between SM thread and/or warp scheduler limits, shared memory usage, register usage, and overall SM count, and those tradeoffs can be counterintuitive if you follow (admittedly, NVIDIA’s official) guidance that maximizing the thread count leads to optimal performance.

Protecting the main branch is definitely a good practice, but the other potential hazard is:

- Having a developer on your team that rebases their own feature branch

- Then tries to "git push", only for it to be rejected since a force push is required

- Then performs a "git push --force", which will force-push all of their local branches, including feature branches from other developers that they may have checked out previously

Our team uses merges because they are safe from this kind of problem, although a rebase workflow would have cleaner history. I wish that "git push --force" would not push all branches by default, and just fail unless a (remote, branch) pair or --all is given.

Difftastic is a useful tool, but in my experience, it's far too slow to be suitable as the default selection for a ubiquitous tool like git.

Whether the technique described here will actually be faster is pretty application-dependent. The problem is that, on x86, shuffle instructions are the bottleneck for many algorithms (at least the type that I often work with). Storing constants this way requires adding an extra shuffle each time that you need to broadcast one of the constants back to a vector register, which exacerbates the bottleneck. In these cases, I’ve found that light spilling to the stack actually performs better.

I have had good luck with fpm, which makes it easy to make packages of all different kinds, including deb and rpm: https://github.com/jordansissel/fpm

From a quick look at Lima, I don't think it's exactly the same thing. Tart allows running macOS and Linux VMs, while Lima seems focused on Linux VMs only. I don't use Tart, but having infrastructure-as-code-like tooling that can be used to define macOS environments (and store the VMs in container registries) sounds useful and I'm not aware of another solution that does it.