kammerdiener

It's not using timing-based aggregation. The EU stall samples from hardware include the instruction pointer, which links them to the shaders mapped in the GPU's address space.

Your explanation was just fine. I was simply asking what else you knew about the technique. Perhaps where you first heard of it or some examples where it has been applied/benchmarked.

Do you have any more info on this?

Unless you spend far too much on more cache per core, you’re going to quickly find that the bottleneck becomes the memory system. Hardly any of these low-priority process that would be scheduled in E cores are actually doing much compute. They’re either blasting memory or I/O, so adding more cores for them doesn’t help much.