irishjohnnie

I believe it is both a scheduling and memory allocation/loading issue. It is interesting that caches are NUMA but main memory is not.

Are you referring to the ballpark "specifications" in the article? If so, I don't know of any material that can withstand the stresses of the weights and speeds mentioned in it ... unless you are going for really low wing loading (think dirigible).

Current inflation is mostly supply-side driven. Having said that, M2's biggest jump in its history was in early 2020 (see https://fred.stlouisfed.org/series/M2SL). Its slope before and after is more or less the same. However, I don't think inflation will lag it by more than a year.

Yup. OceanWings by VPLP https://www.hellenicshippingnews.com/vplp-design-signs-its-f...

> It’s honestly a shame that we didn’t keep pursuing sail technology ...

You mean something like this? https://www.top-yachtdesign.com/oceanwings-by-vplp/

ICYMI lots of issues with that study, https://academic.oup.com/aje/article/doi/10.1093/aje/kwaa155... https://academic.oup.com/aje/article/doi/10.1093/aje/kwaa156...

It also looks like that study is still in the peer review process. It has the "Accepted Manuscript" flag (https://academic.oup.com/aje/pages/Instructions_To_Authors) and has at least one major error, https://academic.oup.com/aje/article/doi/10.1093/aje/kwaa155...

> Covid is an autoimmune disease. The Over active immune response is what is killing people.

The virus triggers an acute immune response. This is not the same as an autoimmune disease, it may be the opposite. Also, people with certain blood types that have better clotting ability seem to be at a disadvantage.

There is also a glaring conflict of interest regarding the author of that paper and some manufacturers of the drugs in question, https://academic.oup.com/aje/article/doi/10.1093/aje/kwaa156...

I missed this in my previous reply ...

> Look at all the results. Even before that exceptions are more often a win than a loss.

The blog post you linked to effectively says "it depends"

> But on 64-bit windows the default exception handling (SEH) uses a similar mechanism than Linux and should have comparable performance.

AFAIK SEH in Windows calls RaiseException() which in turn causes a user/kernel mode transition, probes for exception/termination handlers, and vectored exception handlers depending on the severity. It's been a while but I'm not sure the code GCC generates in Linux is quite like this.

> benchmarks have shown that exceptions are generally faster

The blog post you linked to says "Immediately we see that once the stack depth grows above a certain size (here 200/3 = 66), exceptions are always faster. This is not very interesting, because call stacks are usually not this deep (enterprise Java notwithstanding). For lower depths there is a lot of noise, especially for GCC ..." So ... not exactly "generally faster".

Also, the test is only for Linux. The same test on Windows/VC++ will probably run a lot slower ... again not "generally faster"

Video from SciTech conference https://livestream.com/accounts/6056055/events/8001237/video... starting at around 41 minutes

I was referring to the RTL-based IP that goes into each subsystem of the CPU, hence the analogy to code. You're talking about compiler instruction scheduling, a lot of which are a bunch of non-AI algorithms. If I'm missing something, I would appreciate the references to the functionality you're referring to.

Probably not. Do you use AI to write code?

Wow! AMD EPYC + Xilinx FPGA!

You mean like Xilinx's Zynq? https://www.xilinx.com/products/silicon-devices/soc/zynq-700...

Ring buffers are also used in web servers, database servers, different kinds of device drivers protocol stacks, constrained embedded devices, etc.

IIRC, the data structure that they used was not thread-safe. There eventually had to be an interlocked compare exchange operation which slowed throughput. Also, I couldn't imagine this working correctly in out-of-order cores without memory barriers at the very least.

It's been a while, but didn't the performance turn out to be similar to other data structures in multi-socket scenarios because it requires interlocked -type instructions?

Wouldn't the equivalent of that be a JTAG debugger for the NIC?

I think the closest thing to a Wireshark for CPUs is Intel VTune (https://software.intel.com/en-us/intel-vtune-amplifier-xe)