gdevic
12'b0000_0000_001?: begin : instr_daas // DAA, DAS
if (flags[BF_BIT])
rx[0] <= rx[0] + (op_is_daa ? 4'd6 : 4'd10);
flags[CF_BIT] <= flags[BF_BIT];
state <= FETCH;
end : instr_daasCreating the kind of quality video we're all used to seeing is beyond my skill level and ... motivation.
https://baltazarstudios.com/files/calculator-d/Calculator.ht...
https://baltazarstudios.com/files/calculator/Calculator.html
This WebAsm code is compiled using Qt and Verilator so it runs the "hardware" and its microcode inside the simple UI shell that provides the calc interface. In the debug version you can list the ucode, set breakpoints, see regs etc.
The architectural decision everything else follows from: a decimal calculator should store numbers as BCD — one decimal digit per 4-bit nibble. A standard byte-oriented CPU (Z80, 6502) fights that layout constantly. So I designed a small custom CPU in Verilog where 4 bits is the natural data width and memory is nibble addressable.
What the project covers:
- Custom CPU: Harvard architecture, 12-bit ISA, 8-state execution FSM, hardware stack guard with a FAULT state for microcode debugging
- CORDIC for trig functions, verified to 14 significant digits
- Two-pass assembler in Python (~700 lines)
- Verilator + Qt framework: same Verilog source runs in simulation, as a desktop GUI debugger, as WebAssembly, and on real hardware
- Scripting language on top of the microcode for adding functions without touching hardware
- Custom PCB (EasyEDA/JLCPCB), battery, charging circuit
Write-up: https://baltazarstudios.com
Hackaday: https://hackaday.com/2026/05/13/build-the-cpu-then-build-the...
At this point WSL2 is more than filling this void. I even stopped using VMWare since WSL is that good.