brohee
brohee on Hacker News
Justice can be brought to them tho... At some point someone will delete the building they work in with a cruise missile or two...
What in the history of crypto let you think any kind of sensible practices are followed? It's been a clown show since it started, and no end in sight...
Heavy lift drones are pretty common, a 150kg or more payload is enough for a soldier with his individual equipment. The are pretty short ranged but they only need to reach to a few kms into the grey zone and back.
See e.g. the KF 150 multi copter. And it's sub $50k
Thieves and intelligence agencies can be one and the same, see North Korea... Crypto is especially useful for heavily sanctioned countries.
Do you? Someone actually sell backdoored crypto wallet insurance?
Posted by
brohee on Tuesday October 13, 2026 @12:52PM
from the status.yandex.cloud dept.
Insurance for cyber incidents usually only cover you if you took reasonable measures. Like not exposing your internal systems to the Internet.
Also talking about quantum computers breaking SHA-256 means he knows a lot more than the rest of us or not nearly enough to pipe up about the subject.
"The ARM-based CPU manufacturers make this worse by posting almost no low-level documentation for their CPUs."
Are those not based on standard ARM cores or ARM documentation on its cores not deep enough for your purpose?
Posted by
brohee on Thursday September 10, 2026 @09:03AM
from the blog.mathieuacher.com dept.
The discussion on the cost of the attack needs an addendum. The lattice sieving part would be free for an an attacker with a big enough botnet or enough cloud computing stolen credentials.
Maybe it could even be practical to run it on browser in parallel to video streaming on a free video site...
Not all attackers pay for compute. With enough stolen compute, breaking RSA-1024 is free and not that slow...
Yeah I really wonder what makes them think they are legally insulated from the actions of the agents they ran...
The crimes were relatively benign but Grok going the Silkroad way would be on brand...
Efficiency is not that that important in an era of negative price electricity.
Synfuel made just from air and electricity is doable (both water and carbon dioxyde can be extracted from the atmosphere). And with 10% of what's spend on IA we'd be way out of the lab...
Thankfully there are military budgets (synfuel makes sense on a nuclear carrier)
I've fairly good control over not running my car out of the road, yet I have airbags...
A backdoor in physics would be interesting indeed, but not as likely as a rogue agent in a TSMC fab...
Security-partition switches that carefully reset all shared micro-architectural state, while making switch times completely deterministic, and in particular, independent of previous execution history.I'm afraid it means clearing all caches at each context switch. The performance penalty is really high.
I don't think you can ignore memory access. The whole "hyperthreading considered harmful" was because of shared cache between contexts. That's why I think a proof is in reach without cache, much harder with one...
I'm not so sure. It's pretty hard to know how many cycles a register load instruction will take if there is a cache, or worse a cache hierarchy. That's why I think it will be a lot easier to have a proof on simple cache less designs...
Your version is likely good enough in practice though.
This has its own issues. Big bad actors can now split their activities between more smaller companies to avoid some regulation. I've seen it happening.
To add to that, the only way I see proof of absence of timing channels is by proving both the software and the hardware design side by side, and then the proof would hold only for a specific core. Something that would look both at the code manipulating secrets and at the Verilog for the specific core/memory chips. I've not been working in that space in a long while but AFAIK such a thing is nowhere near ready. I suspect it will be a lot easier if the hardware design is optimised for provability, which won't be good at all for performance. But there are plenty of contexts where security matters a lot more than performance (SMC, BMC, RoT and co at the very least).
And then you'd need assurance that the Verilog is faithfully transcribed in the silicon, which is a can of worms in itself.
The assumptions the proof makes are pretty clearly listed:
https://sel4.systems/Verification/assumptions.htmlThe one covering side channels is pretty honest:
Information side-channels: this assumption applies to the confidentiality proof only and is not present for functional correctness or integrity. The assumption is that the binary-level model of the hardware captures all relevant information channels. We know this not to be the case. This is not a problem for the validity of the confidentiality proof, but means that its conclusion (that secrets do not leak) holds only for the channels visible in the model. This is a standard situation in information flow proofs: they can never be absolute. As mentioned above, in practice the proof covers all in-kernel storage channels but does not cover timing channels.
So the proof won't be invalidated at it does not cover that particular threat.
Now the question is how useful the is a proof not covering side channels? I'd say pretty useful and it doesn't mean they don't have counter measures for to counter their exploitation, nor that they are not effective, just that a proof of efficiency is out of reach for now.
I suspect a lot of software does not behave well at negative altitude. I heard of an ECU having trouble on one of the rare negative altitude roads.
SCEP was (and still is) a very deployed protocol yet took 20 years for the draft to be published...
Writing multiple pages for a few hundred actual bytes also thrashes the OS cache...
Ah, the Ulrich Drepper school of dealing with reported issues. Time for esystemd ;)