beautifulpeople
beautifulpeople on Hacker News
Re:Trump Administration Preps Plan for Huge Cuts to Department of Energy
on Wednesday January 25, 2017 @11:31AM (#13482809)
China is going to be one happy country.
Re:Getting to Bootstrap v4
on Tuesday September 06, 2016 @10:36AM (#12436268)
>attitude that a piece of software can never simply be finished
The problem often is the delta between perfect, and done. It's hard, as a creator, to realize when something is great in other people's eyes. The creator looks at their work and cringes. Everyone else looks at it and claps. It's that delta that creates the drive for perpetual development.
Re:ARM v8-A with Scalable Vector Extensions: Aiming for HPC and Data C...
on Monday August 22, 2016 @08:33AM (#12335839)
Also, remember that we're all DDR burst length limited. Unless you change the DDR model, most are 8 bytes x N-length so you'll only get 64-bytes unless you can get the standard changed. If you think about re-use of cache lines though, for most apps part of the data will be in cache and part of it will not be. so likely 64-byte lines will still work well for most applications, it'll be interesting to see what ARM and their partners do going forward. Intel it seems has gone the HMC route, wonder how many others will follow the same route.
Re:ARM v8-A with Scalable Vector Extensions: Aiming for HPC and Data C...
on Monday August 22, 2016 @08:29AM (#12335817)
Looking at the article, I'm not sure 2048-bit lines are quite needed (not to say that that wouldn't be interesting), from (http://www.theregister.co.uk/2016/08/22/armv8_scalable_vecto...): "And once a program has been built for SVE, it will run comfortably on any SVE-capable processor without recompilation, whether the CPU has support for 512, 1,024 or the full 2,048 bits. The SVE unit can automatically break a 2,048-bit vector into, say, four 512-bit vectors if its silicon implementation doesn't support the full length." This paragraph from The Register implies that you could have smaller chunks or larger depending on the silicon implementation. If you look at a 64-byte cache line (what most architectures have today, power & itanium are notable exceptions) that would mean 512-bits per line (assuming you can use the whole line, i.e. packed). For 2048-bit that means 4 cache lines worth of data could potentially be operated on at once.
Re:China's Hybrid Spaceplane Could Reset the 21st Century Space Race
on Friday August 12, 2016 @02:10AM (#12273660)
If it's anything like they're over-traffic bus then I doubt it. It'll probably have a home AC unit bolted to the outside, and some "hybrid" roman candles for propulsion.
Re:Dem-owned-crats: Now its congressional committee is hacked
on Saturday July 30, 2016 @10:00AM (#12192987)
hacking while rich....he'll never be charged.
Re:Fujitsu Switches Horses for Post-K Supercomputer, Will Ride ARM int...
on Saturday July 02, 2016 @01:15PM (#12023144)
I think you're missing the big picture here. Looks like Cray has been looking at ARM for awhile for Fast Forward 2 (US DoE I think, announced 2014: http://investors.cray.com/phoenix.zhtml?c=98390&p=irol-newsA...). Looks like Barcelona Supercomputing Center also deployed ARM based test systems quite awhile ago (http://nvidianews.nvidia.com/news/barcelona-supercomputing-c..., http://gizmodo.com/5898633/can-an-arm-based-supercomputer-be...).