Lind5

part 2 of this series https://semiengineering.com/rethinking-memory/

"In addition to increasing capacity and speed, the improvements in energy efficiency are noteworthy. With HBM3, the core voltage is 1.1V, compared to HBM2E’s 1.2V core voltage. HBM3 also reduces the I/O signaling to 400mV versus 1.2V for HBM2E. There will be further improvements in future generations, as well."

may even go to FP4 standard!

AI already has led to a rethinking of computer architectures, in which the conventional von Neumann structure is replaced by near-compute and at-memory floorplans. But novel layouts aren’t enough to achieve the power reductions and speed increases required for deep learning networks. The industry also is updating the standards for floating-point (FP) arithmetic. https://semiengineering.com/will-floating-point-8-solve-ai-m...

Astounding amount of semi investments. $500B in this list alone https://semiengineering.com/where-all-the-semiconductor-inve...

Software engineers looking for a job should consider the chip industry, which is not just about hardware engineers. Plenty of software engineer openings https://semiengineering.com/jobs/ and many are remote

this related article addresses some of the cost issues https://semiengineering.com/designing-ics-in-an-increasingly...

Dealing with the exponential increase in data is driving some massive architectural changes. This Univ of Penn research is interesting. Chip companies are currently working a number of strategies. Related: https://semiengineering.com/ic-architectures-shift-as-oems-n...

not just the chip shortage. The rise of RISC-V coincides with a couple of other events in the industry. The first is the slowing of Moore’s Law, meaning that increases in total processing power no longer comes along with each new fabrication node. The second is the meteoric rise in machine learning, demanding massive increases in processing power. https://semiengineering.com/why-risc-v-is-succeeding/

More info here from the discoverers at ETH Zurich https://comsec.ethz.ch/research/microarch/retbleed/ and here is the actual technical paper https://comsec.ethz.ch/wp-content/files/retbleed_sec22.pdf

Semiconductor Engineering does a monthly startup funding report. All are chip industry related

https://semiengineering.com/knowledge_centers/startups/

Hybrid bonding big part of this https://semiengineering.com/hybrid-bonding-moves-into-the-fa...

Intel’s support for RISC-V marks a technological and cultural shift https://semiengineering.com/which-processor-is-best/

also relevant & more recent https://semiengineering.com/reliability-concerns-shift-left-...

title was too long. Here it is "A Deeper Look into RowHammer’s Sensitivities: Experimental Analysis of Real DRAM Chips and Implications on Future Attacks and Defenses"

"The practice of “zero trust” is particularly important here. Any device or software outside the organization cannot be trusted". Great approach but it is amazing how many breaches are still happening due to lack of basic prevention measures taken