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A comment on Show HN: A pipelined RISC-V processor written in VHDL. Parent comment

Re:Show HN: A pipelined RISC-V processor written in VHDL by sklogic on Wednesday July 29, 2015 @05:02AM (#9967219)
or1k used a very simple approach - duplicate all the pipeline registers in all the stages and use two register files. Then store the current state once interrupt is raised and restore when handler done working. This design can be easily derived from an existing one.
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