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A comment on The Itanium processor, part 1: Warming up. Parent comment

Re:The Itanium processor, part 1: Warming up by nickpsecurity on Monday July 27, 2015 @02:12PM (#9956935)
It's a very interesting architecture that I've heard about on paper for a while now but never seen on silicon. Have they done anything with it on ASIC/FPGA or is it vaporware for now?

Talking exotic, look at No Instruction Set Computing (NISC) which was at least prototyped and published synthesis/compilers:

https://web.archive.org/web/20080302041756/http://www.ics.uc...

Really interesting stuff. Reminded me of Tensillica's tools that create a custom processor for your application. Need to accelerate your Hadoop, etc application? Run most of it on Intel CPU with an onboard FPGA & NISC tools doing the critical path. Intel's Altera acquisition might make something like that achievable in future.

Note: Used archive because their site is having a configuration error.

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Re:The Itanium processor, part 1: Warming up by WallWextra on Monday July 27, 2015 @04:36PM (#9957837)
Last I heard, the Mill guys don't even have a compiler working, but do have a simulator. Not sure what they're simulating.
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Re:The Itanium processor, part 1: Warming up by wtallis on Monday July 27, 2015 @05:53PM (#9958267)
Their June talk was about their compiler and toolchain, which borrows heavily from LLVM. It's almost certainly not done, but they do have something more than just an assembler. They've also started working on implementing it for FPGA, but only as a proof of concept rather than something intended to be ready to make into an ASIC.
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