Re:Pebble Time Smartwatch Teardown
by quadrature on Saturday July 04, 2015 @11:29AM
(#9830427)
Got to love Dave's commentary, Always learn a thing or two from his teardowns.
I wonder if anyone from pebble can comment on the FPGA, I thought that was a bit odd as well, Is it just so that the processor can sleep as much as possible and doesnt have to wake on small trivial things ?.
Re:Pebble Time Smartwatch Teardown
by ctz on Saturday July 04, 2015 @12:21PM
(#9830597)
Probably to drive the memory LCD. The drive timing in the datasheet looks pretty tight (about 2.2MHz), and bit banging at that rate will leave the uC unable to much else during a screen update. Ideally, you want to make use of the STM32F439's 2D graphics accelerator to do graphics legwork, then the DMA controller to write out to the screen.
The FPGA could even have been provided by the LCD vendor to provide a more standard interface.
Re:Pebble Time Smartwatch Teardown
by ju-st on Saturday July 04, 2015 @11:47AM
(#9830477)
Yeah, I think it may be used for the actual watch feature (displaying the time) and display control so the main processor can sleep almost all the time.
Re:Pebble Time Smartwatch Teardown
by TeMPOraL on Saturday July 04, 2015 @12:16PM
(#9830571)
Literally few hours ago I was reading Pebble and Pebble Time teardowns on iFixIt, and this FPGA captured my attention as well. I'd really like to know what function it serves there.
I wonder if anyone from pebble can comment on the FPGA, I thought that was a bit odd as well, Is it just so that the processor can sleep as much as possible and doesnt have to wake on small trivial things ?.
The FPGA could even have been provided by the LCD vendor to provide a more standard interface.
https://www.reddit.com/r/pebble/comments/37lg95/ifixit_pebbl...