Note that you don't need a dumb compiler, register pressure, or an instruction with physical register constraints to require a copy. Two-address instructions suffice: simply have a register for the first operand that contains a value that is used later. A copy is required to preserve the value stomped by the mutating instruction.
In any case I believe the point of the GP is that any necessary copy can be done by going through memory, so register-register moves can be dispensed with where minimalism is the goal.
Re:X86 mov is turing complete: mov-only compiler
by rdc12 on Saturday June 20, 2015 @09:34PM
(#9751745)
Do you have a citation for the 168GP registers, just wondering if Intel have "offically" stated the number they use in a given microarch.
Re:X86 mov is turing complete: mov-only compiler
by pbsd on Saturday June 20, 2015 @10:09PM
(#9751838)
You can find an official Intel source for Haswell in here (page 15): http://pages.cs.wisc.edu/~rajwar/papers/ieee_micro_haswell.p...
Re:X86 mov is turing complete: mov-only compiler
by sp332 on Saturday June 20, 2015 @10:19PM
(#9751868)
I might be misreading this, but I think it's on slide 24 of this PDF http://www.hotchips.org/wp-content/uploads/hc_archives/hc25/...
Of course, modern processors don't really care about register-register moves because they have hundreds of hidden intermediate registers and register renaming which makes those types of moves "free." (e.g. Haswell has 168 GP registers, only 16 of which are exposed through the AMD64 ISA.)