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Re:Designing a CPU in VHDL, Part 1: Rationale, Tools, Method by domipheus on Friday June 19, 2015 @04:26AM (#9743580)
Thanks for the advice! I've been synthesizing a bit, fixing a few issues that at least didnt present when building for the simulator. I've yet to run it actually on hardware, though - that part will be fun. Webpack does still come with the schematic viewer, which is really neat.

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