Re:Designing a CPU in VHDL, Part 1: Rationale, Tools, Method
by domipheus on Friday June 19, 2015 @04:22AM
(#9743569)
Cheers for the tips. I'll eventually move to Verilog, but as others point out, I think it's good to walk before I run. Regarding pipelining, I'm getting right on it - and the iterative benchmarking is something I plan to do. Thanks again :)
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Re:Designing a CPU in VHDL, Part 1: Rationale, Tools, Method
by alain94040 on Friday June 19, 2015 @11:48AM
(#9745557)
Also, feel free to contribute to the Verilog tutorial I started for software engineers, it's on WikiBooks at https://en.wikibooks.org/wiki/Programmable_Logic/Verilog_for...
VHDL is dead in the industry(). While VHDL is slightly better for teaching, why not learn directly what everyone else uses? Also, because VHDL is such a pain to support for CAD tools, more tools support Verilog only, or support VHDL as a second-class citizen.
() my european friends hate me each time I say that, but it's true.
Re:Designing a CPU in VHDL, Part 1: Rationale, Tools, Method
by hobolord on Friday June 19, 2015 @03:12PM
(#9746984)
Yeah I was taught in VHDL but my prof acknowledged that it's mainly because it's better as an educational tool. He argued that it's easier to go from VHDL to Verilog after learning the strict practices, and that it leads to just better programming practices in the industry