Re:The Intel Xeon E7-8800 v3 Review: The POWER8 Killer?
by dragontamer on Wednesday May 13, 2015 @11:10AM
(#9539489)
Indeed. Which is why I've been keeping up with AMD's HSA news. Their GPUs that share L2 Cache with the CPU intrigue me. After all, if you're piping data back and forth between the GPU / CPU, all sorts of applications open up.
Unfortunately, there's no real scaling. The APUs are mostly consumer products. The biggest APUs are XBox One and PS4, unavailable to the public.
Still, its nice to see a company tackle the latency issue.
I published a paper with this conclusion a while back ("Evaluation of Streaming Aggregation on Parallel Hardware Architectures", http://www.scott-a-s.com/files/debs2010.pdf). My paper was basically, "GPUs are awful for our problem, so let's compare to CPUs and Cell". A more recent paper from NSDI 2015 from a group at CMU, with Anuj Kalia as the first author, that also looks into it, "Raising the Bar for Using GPUs in Software Packet Processing", http://www.cs.cmu.edu/~akalia/doc/nsdi15/gopt_nsdi.pdf. They look at just the GPU and CPU part of the spectrum - which is probably more relevant to most, as the Cell is a dead technology now. (I think my conclusions will matter more when on-chip GPUs become more prevalent, but we're not there yet). Their paper starts with an excellent analysis of the latencies for transferring data to GPUs, and comparing end-to-end performance against several different algorithms, where they vary the amount of data reuse.
My consistent gripe when talking about improving application performance by using accelerators is that one must take data copying costs into consideration, which means we must use application end-to-end performance as our metric. There's a temptation to focus on just the computational kernel performance. The Kalia et al. paper is the best treatment of this subject that I have seen.