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A comment on The J1 Forth CPU. Parent comment

Re:The J1 Forth CPU by eggy on Tuesday April 14, 2015 @12:37AM (#9372136)
I am new to FPGAs. I have a Terasic DE0 Nano. Would I be able to get the J1 running on it with the Verilog code, or do I need to translate it? Does the DE0 Nano have what it takes? I appreciate if you could answer my beginner questions. Thanks.
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Re:The J1 Forth CPU by mng2 on Tuesday April 14, 2015 @01:28PM (#9375847)
You'll need to change the RAM primitive to the Altera equivalent, but it should fit just fine. Then you have to figure out how you're going to interface to it.
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